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09449PV
CY7C09449PV-AC
128 Kb Dual-Port SRAM with PCI Bus Controller (PCI-DP)
Features
* 128 Kb of dual-ported shared memory * Master and Target PCI Specification 2.2 compliant interface * Embedded host bridge capability * Direct interface to many microprocessors * I2O message transport unit; includes four 32-bit, 32entry FIFO * Local bus clock rates up to 50 MHz * Single 3.3V Power Supply including compatibility with 3V and 5V PCI Bus signaling * 160-pin thin plastic quad flat package A primary resource within the CY7C09449PV is its 128 Kb of dual-port memory. This memory is interfaced to both the PCI bus and to a local microprocessor bus. This shared memory can be accessed as a target from both buses at the same time for inter-process communication. From either the local or PCI bus the CY7C09449PV can be directed to become a PCI bus master to move data into or out of the internal shared memory as a direct memory access (DMA). The CY7C09449PV can DMA across the PCI bus any number of 32-bit double words (DWORD), up to 16K bytes. It uses the full bursting capabilities of the PCI bus for maximum efficiency and can transfer data over the full 32-bit PCI address space. The CY7C09449PV implements optional requirements of the PCI specification by selecting the optimum PCI command for each transaction it masters to the PCI bus. This maximizes overall efficiency of the system platform. PCI bridging functions (PCI-to-PCI and Host-to-PCI bridges) use the commands to enhance prefetch and cache coherency operations. The CY7C09449PV requests and gains access to the PCI bus as any master. It does not, within itself, include a PCI bus arbitration function. Standard PC PCI buses include this function; embedded systems may need to implement this function. The CY7C09449PV provides a direct access mechanism from the local bus to the PCI bus. With it, the local processor can direct the CY7C09449PV to run a PCI bus master cycle of any kind to any address. This means that the CY7C09449PV can run PCI configuration cycles allowing it to be used as a host bridge.
Introduction
The CY7C09449PV is one of the PCI interface controllers in the Cypress Semiconductor PCI-DPTM family. The CY7C09449PV provides a PCI master/target interface with direct connections to many popular microprocessors. It provides 128 Kb of dual-port SRAM that is used as shared memory between the local microprocessor and the PCI bus. An I2O message unit, complete with message queues and interrupt capability, is also provided. The CY7C09449PV allows the designer to interface an application to the PCI bus in a straightforward, inexpensive way.
Functional Overview
The CY7C09449PV is composed of a number of shared resources that allow effective data movement between the local bus and the PCI bus.
Table of Contents Features Introduction Functional Overview Pin Configuration Pin Description PCI Bus Local Bus Timing Diagrams I2C Serial Port and Auto-Configuration Operations Registers Performance Characteristics CY7C09449PV Operations Ordering Information Package Diagram 1 1 1 4 5 9 12 16 27 29 41 46 48 48
Cypress Semiconductor Corporation Document #: 38-06061 Rev. *A
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised December 27, 2002
CY7C09449PV-AC
Bus Master/Slave Interface
Up to 16 KByte Burst Transfers on PCI Bus
User-Configurable Target Interfac (Supports Burst Mode)
Local Processor Bus Interface
PCI 2.2 Bus Interface
128 Kb Dual-Port Shared Memory
Local Bus
PCI Bus
I2O Message Transport Unit
Operations Registers
I2C
SCL/SDA
PCI-DP
TM Allows Local Processor Provides Required FIFOs and Direct Access to PCI Bus Interrupt Status Registers
AN3042_BD.vs
Four First-In First-Out (FIFO) storage elements provide another resource to the user. These are accessible from either the PCI bus or the Local bus. When the I2O messaging unit functionality of the CY7C09449PV is to be used, the four FIFOs become part of the I2O messaging unit of the CY7C09449PV. The I2O messaging unit consists of the four FIFOs and the I2O system interrupt registers. The shared memory of the CY7C09449PV may be used to store I2O message frame buffers while most of shared memory is still available for generals purpose use. Efficient I2O messaging is realized when the local processor uses the CY7C09449PV direct access mechanism. It can be used to retrieve and post I2O message pointers to other I2O agents. Data transfer of the messages themselves is made very efficient using the CY7C09449PV PCI DMA controller to burst the message frames to other I2O agents. Interprocess communication is supported by two resources of the CY7C09449PV: the mailbox registers and the arbitration flags. By writing to the mailbox registers, a method is available for the local processor to pass data while causing an interrupt to the host, and vice versa. This is enabled by the interrupt mask located in the CY7C09449PV Operations Registers. The arbitration flags are four pairs of bits that can be used to manage resource allocation and sharing between software and system processes. The CY7C09449PV includes an interrupt controller. There are separate interrupt mask and command/status registers for the
PCI bus and the Local bus. The interrupt sources are DMA completion, mailbox, FIFO not empty (also for I2O), FIFO overflow, PCI master abort, PCI target abort, and there is an external interrupt input pin. This interrupt controller is used to signal interrupts onto the PCI bus and the Local bus. The CY7C09449PV interrupt controller does not perform the interrupt controller function for the PCI bus system. Standard PC PCI systems include this function; embedded systems may need to implement this function. An I2C-compatible serial interface is provided to allow the use of a serial EEPROM for non-volatile storage of CY7C09449PV initialization parameters. The parameters are PCI configuration and local bus settings. The CY7C09449PV will optionally access the EEPROM after reset and download initialization information before responding to PCI or local bus transactions. A wide variety of available I2C-compatible serial components are available to the local and host processor when connected through this interface. The CY7C09449PV local bus is a flexible, configurable interface that is designed to readily connect to many industry standard microprocessors. In most cases, no external interface logic ("glue") is needed. The following block diagram illustrates a generic application for the CY7C09449PV.
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CY7C09449PV-AC
PCI Add-In Card or PCI System Host
Processor Power QUICC, 80x86, DSP, etc. CY7C09449PV
PCI System Bus
128K Bit Shared Memory
Memory SRAM, DRAM, FLASH, etc.
Processor Local Bus
Peripherals Mass Storage, ATM, Special, etc.
3042APP.VSD DB 6/02
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CY7C09449PV-AC
Pin Configuration
160-Lead TQFP (A160) for CY7C09449PV Top View
BE[0] BE[1] BE[2] BE[3] VDD8 VSS11 CLKIN VSS10 PCLKOUT2 PCLKOUT1 PCLKOUT0 RDY_OUT RDY_IN RDY_IN WRITE READ BLAST VSS9 DQ[31] DQ[30] DQ[29] VDD7 VSS8 DQ[28] DQ[27] DQ[26] DQ[25] DQ[24] DQ[23] DQ[22] DQ[21] VDD6 VSS12 VDD1 ADR[8] ADR[7] ADR[6] ADR[5] ADR[4] ADR[3] ADR[2] VSS1 ALE IRQ_IN IRQ_OUT VSS2 VDD2 RSTOUTD RSTOUTD RSTOUT VSS3 SELECT SDA SCL TEST_MODE INTA RST CLK VSSP1 VDDP1 GNT REQ AD[31] AD[30] AD[29] VSSP2 VDDP2 AD[28] AD[27] AD[26] AD[25] AD[24] VDDP3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 ADR[9] ADR[10] ADR[11] ADR[12] ADR[13] ADR[14] STROBE
160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
VSS7 DQ[20] DQ[19] DQ[18] DQ[17] DQ[16] DQ[15] DQ[14] VDD5 VSS6 DQ[13] DQ[12] DQ[11] DQ[10] DQ[9] DQ[8] DQ[7] VDD4 VSS5 DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] VDD3 VSS4 AD[0] AD[1] AD[2] AD[3] VDDP8 VSSP8 AD[4] AD[5] AD[6] AD[7] C/BE[0] VDDP7
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VSSP3 C/BE[3] IDSEL AD[23] AD[22] NC1 AD[21] AD[20] AD[19] VSSP4 VDDP4 AD[18] AD[17] AD[16] C/BE[2] NC2 FRAME IRDY TRDY VSSP5 VDDP5 DEVSEL STOP PERR NC3 SERR PAR C/BE[1] AD[15] VSSP6 VDDP6 AD[14] AD[13] AD[12] AD[11] AD[10] AD[9] AD[8] NC4 VSSP7
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CY7C09449PV-AC
Pin Description
The Pin Type for CY7C09449PV is defined as follows: in out t/s s/t/s Input is a standard input-only signal. Standard output driver. Three-state is an output or bidirectional signal. Sustained Three-State is an active LOW, three-state capable signal driven by only one bus agent at a time. When ownership is passed to another agent, the signal is driven HIGH for one clock, and then three-stated for an additional clock before being driven by the new owner. Open Drain signals allow multiple devices to share the pin as a wired-OR. Open Collector signals allow multiple devices to share the pin as a wired-OR.
o/d o/c
PCI Bus Signals Signal Name CLK RST AD[31:0] Type in in t/s Description Clock: This is the PCI Bus clock and is the timing reference for all PCI bus transactions. The CY7C09449PV can operate with a 33-MHz PCI bus interface. RESET: This signal is the PCI bus reset. It is one of the few PCI signals which may be asserted or deasserted asynchronously to the PCI bus clock (CLK). Address and Data: These signals represent the PCI bus address and data signals multiplexed on the same PCI pins. Information on these pins is identified as an address during the clock cycle in which the signal FRAME is first asserted. This is termed the "address phase" of a bus transaction. Information on these pins represents valid read or write data when both IRDY and TRDY are asserted, based on the current cycle type as defined on the C/BE lines during the address phase. This condition is termed the "data phase" of a bus transaction. Command and Byte Enables: These pins are used with the AD[31:0] pins. During the address phase of a bus operation, they identify the bus command to be performed. During the data phase of a bus operation they identify which bytes are involved. Parity: This PCI bus pin represents the even parity across the A/D[31:00] and C/BE[3:0] pins (36 pins) and is generated with a one clock delay. Cycle Frame: This PCI bus pin is asserted by the current bus master to signify the beginning of a bus transaction. Data transfers may continue in burst mode while FRAME remains asserted. When FRAME is deasserted it indicates that the transaction is in the final data phase. Initiator Ready: This signal is driven by the current bus master (initiator) and asserted to indicate its ability to complete the current data phase. Data is transferred when both IRDY and TRDY are asserted, otherwise wait cycles will occur. Target Ready: This signal is driven by the selected bus target and asserted when that target is ready to complete the current data phase. Data is transferred when both IRDY and TRDY are asserted, otherwise wait cycles will occur. Stop: The STOP signal is driven by the selected bus target and is asserted when it wishes to cease the current data transaction. Initialization Device Select: This signal is used to gain access to the PCI configuration register space of a given PCI Bus agent. Device Select: The DEVSEL signal is driven and asserted by the currently selected PCI bus target based on the current address and that target's assigned address range. Bus masters examine this signal to determine whether the desired device is present.
C/BE[3:0]
t/s
PAR FRAME
t/s s/t/s
IRDY
s/t/s
TRDY
s/t/s
STOP IDSEL DEVSEL
s/t/s in s/t/s
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CY7C09449PV-AC
PCI Bus Signals (continued) Signal Name REQ GNT PERR SERR INTA Type t/s t/s s/t/s o/d o/d Description Request: This signal indicates to the bus arbiter that this device wishes to use the bus. It is a pointto-point signal that is driven whenever RST is not asserted. Grant: This point-to-point signal indicates that the bus has been granted to the requester. It is driven whenever RST is not asserted and is ignored during the assertion of RST. Parity Error: This signal indicates that a parity error has occurred. It is driven by the target or master that is the receiver of data at the clock after the PAR signal becomes valid. System Error: This open drain signal is driven by any device that detects odd parity during an address phase. Interrupt A: This signal is asserted when interrupt servicing of the CY7C09449PV device is required. The INTA pin is a shared PCI bus signal and utilizes an open-drain element to allow a wired-OR.
Local Bus Interface Signals Signal Name ADR[14:2] BE[3:0] Type in in Description Address: These signals identify the local memory location. When the local processor outputs multiplexed address and data, those lines need to be tied to both the DQ[14:2] and ADR[14:2]. Byte Enables: The Byte Enable inputs identify the specific bytes involved in an access. The pins may be configured as byte lane enables, directly, or used as size and encoded byte lane enables when interfacing to certain Motorola processors; see the Local Bus section for definition. Data: CY7C09449PV data input and output are provided on these bidirectional pins. This bus remains in high impedance during power-up and active Reset (RST) and only drives during read transactions. Chip Select: This signal must be asserted for the full duration of any access. The polarity is programmable; the default is active LOW. Address Latch Enable: The local address provided on ADR[14:2] is latched on the trailing edge (from active to inactive) of this signal. The polarity is programmable; the default is active HIGH. Address Strobe: The assertion of this signal begins a memory access and indicates that a valid address has been latched through ALE or is provided at the pins (if ALE is not used and is tied active). The address is provided on the ADR[14:2] pins (during non-multiplexed mode), or on the DQ[14:2] (during multiplexed mode). Outside the address phase, the level of STROBE is don't care.The polarity is programmable; the default is active LOW. Write and Read Signals: These signals control the transfer of data to and from the local data bus. WRITE and READ are sampled in the address phase and are don't cares during the remainder of the bus transaction. The polarity and function of these signals is programmable so that they can be interfaced to processors that support WR/RD or RD/WR, as well as separate RD/RD and WR/WR signals. Burst Last: The signal indicates the end of a burst transfer. This signal has two modes. It can be active during the burst and go inactive when the burst is over, or it can go active during the last data phase of the burst. The polarity is programmable; the default is active LOW. Ready In: The assertion of these signals indicates that the local processor is prepared to complete the current data transaction. Ready Out: When this signal is asserted it indicates that the CY7C09449PV is ready to complete the current access. The polarity is programmable; the default is active LOW. This signal is also programmable to three-state when inactive; the default is to three-state when inactive.
DQ[31:0]
t/s
SELECT ALE STROBE
in in in
WRITE READ
in
BLAST
in
RDY_IN RDY_IN RDY_OUT
in out or t/s
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CY7C09449PV-AC
Local System Signals Signal Name PCLKOUT2 PCLKOUT1 PCLKOUT0 CLKIN Type out Description Clock Outputs: These pins provide three buffered copies of the PCI bus clock.
in
Clock In: This pin provides the timing reference for local bus signals. The CLKIN pin can be driven by an external clock. Also, one of the buffered copies of the PCI clock, PCLKOUT[2:0], may be used as input to CLKIN. This clock must be toggling for proper start-up operation of the CY7C09449PV as well as for PCI access to resources other than the dual-ported shared memory. Reset Out: This pin provides a buffered version of the PCI bus signal, RST. Reset Out Delayed: These pins are similar to the RSTOUT pin described above, however RSTOUTD and RSTOUTD remain asserted until released by the host interface via software control. This allows the CY7C09449PV to hold the local processor in reset until the host processor is ready to release it. Interrupt Request Out: This signal may be used to trigger an interrupt on the local microprocessor. A variety of host-triggered events can be used to cause the assertion of this interrupt request output. This signal may be masked using the Local Interrupt Control/Status Register. When in the inactive state, this signal is three-stated. The polarity is programmable; the default is active LOW. Interrupt Request In: This signal, when asserted, will result in the CY7C09449PV driving the PCI bus INTA signal and therefore cause an interrupt of the host system. This signal may be masked using the Host Interrupt Control/Status Register. Test Mode: When HIGH, this pin puts the CY7C09449PV into a factory test mode. When HIGH and READ is LOW, all outputs are set to high impedance except RDY_OUT will continue to drive if Operations Register LBUSCFG bit 16 is `0'. This is the only test mode available to the user. The user must drive this signal LOW if unused.
RSTOUT RSTOUTD RSTOUTD
out out
IRQ_OUT
t/s
IRQ_IN
in
TEST_MODE
in
Local Configuration Signals Signal Name SCL SDA Power Pins Signal Name VSSP1-VSSP8, VSS1-VSS12 VDDP1-VDDP8, VDD1-VDD8 Other Pins Signal Name NC1-NC4 Type NC Description No Connect: These pins are not to be used; leave unconnected. tion 4.3, System (Motherboard) Specification, of the PCI 2.2 specification for detailed requirements. All Local System and Local Bus Interface input signals must be driven at all times. If they are unused inputs, then they may be driven either HIGH or LOW (pull-up or pull-down, VDD or Ground). SCL and SDA must have a pull-up in the range of 2.2 k to 10 k to VDD. These pull-ups are required whether the signals are to be used or not. Type GND POWER Description Ground: These pins are ground pins (0 volts). Power: These pins provide power, nominally 3.3 volts. Type o/c o/c Description Serial Clock: This pin is the clock output to be used with an external I2C-compatible serial memory device. A pull-up resistor is required. Serial Data: This pin is the bidirectional data pin to be used with an external I2C-compatible serial memory device. A pull-up resistor is required.
Signal Terminations PCI Bus signals should be terminated according to the PCI 2.2 specification. Generally, termination is provided by the PCI system. If the CY7C09449PC is used as a PCI add-in card or other device as part of a PCI bus, no termination should be used. For embedded systems, then terminations are part of the system design; they are not particular to the CY7C09449PV. Any PCI system must include a single pull-up on each PCI bus control signal used. These signals are FRAME, TRDY, IRDY, DEVSEL, STOP, SERR, PERR, LOCK, INTA, INTB, INTC, INTD, REQ64, and ACK64. Refer to Sec-
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CY7C09449PV-AC
Pin List
Pin Name VDD1 ADR[8] ADR[7] ADR[6] ADR[5] ADR[4] ADR[3] ADR[2] VSS1 ALE IRQ_IN IRQ_OUT VSS2 VDD2 RSTOUTD RSTOUTD RSTOUT VSS3 SELECT SDA SCL TEST_MODE INTA RST CLK VSSP1 VDDP1 GNT REQ AD[31] AD[30] AD[29] VSSP2 VDDP2 AD[28] AD[27] AD[26] AD[25] AD[24] VDDP3 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Name VSSP3 C/BE[3] IDSEL AD[23] AD[22] NC1 AD[21] AD[20] AD[19] VSSP4 VDDP4 AD[18] AD[17] AD[16] C/BE[2] NC2 FRAME IRDY TRDY VSSP5 VDDP5 DEVSEL STOP PERR NC3 SERR PAR C/BE[1] AD[15] VSSP6 VDDP6 AD[14] AD[13] AD[12] AD[11] AD[10] AD[9] AD[8] NC4 VSSP7 No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin Name VDDP7 C/BE[0] AD[7] AD[6] AD[5] AD[4] VSSP8 VDDP8 AD[3] AD[2] AD[1] AD[0] VSS4 VDD3 DQ[0] DQ[1] DQ[2] DQ[3] DQ[4] DQ[5] DQ[6] VSS5 VDD4 DQ[7] DQ[8] DQ[9] DQ[10] DQ[11] DQ[12] DQ[13] VSS6 VDD5 DQ[14] DQ[15] DQ[16] DQ[17] DQ[18] DQ[19] DQ[20] VSS7 No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Pin Name VDD6 DQ[21] DQ[22] DQ[23] DQ[24] DQ[25] DQ[26] DQ[27] DQ[28] VSS8 VDD7 DQ[29] DQ[30] DQ[31] VSS9 BLAST READ WRITE RDY_IN RDY_IN RDY_OUT PCLKOUT0 PCLKOUT1 PCLKOUT2 VSS10 CLKIN VSS11 VDD8 BE[3] BE[2] BE[1] BE[0] STROBE ADR[14] ADR[13] ADR[12] ADR[11] ADR[10] ADR[9] VSS12 No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
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CY7C09449PV-AC
Memory Map CY7C09449PV resources are accessed from the PCI bus as an offset from Base Address Register 0 (BAR 0), unless otherwise indicated. Resources are also accessed from the Local bus when the SELECT pin is active. PCI I/O access to this memory map is also available via PCI I/O pointers located at Base Address Register 1 (BAR 1). The memory map covers a continuous 32KB address space. Memory Contents I2O Specific Registers Operations Registers reserved Direct Access to PCI Bus (this is a window into PCI space; this window is only available to the Local bus) Shared Memory Address [14:0], Byte Offset 0x0000 - 0x03FF 0x0400 - 0x07FF 0x0800 - 0x1FFF 0x2000 - 0x3FFF Size 1 KB 1 KB 6 KB 8 KB
PCI Bus
The PCI bus of the CY7C09449PV operates per the PCI Specification revision 2.2. This section describes the specific PCI functions supported by the CY7C09449PV. Reference URL: http://www.pcisig.com/
0x4000 - 0x7FFF
16 KB
PCI Configuration Space
PCI Configuration Space 31 Device ID, RO Status, CS Class Code, RO BIST (not used) 0x00 16 15 Vendor ID, RO Command, CS Revision ID, RO 0 Address, Byte Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 Subsystem Vendor ID, RO 0x0000 0x2C 0x30 0x34 0x38 MIN_GNT, RO Interrupt Pin, RO Interrupt Line, RW 0x3C
24
23 Header Type 0x00
Latency Timer, RW
8
7 Cache Line Size, RW
Base Address Register #0 -- 32KBytes Memory Space, RW Base Address Register #1 -- 8 Bytes I/O Space, RW Base Address Register #2 (not used) Base Address Register #3 (not used) Base Address Register #4 (not used) Base Address Register #5 (not used) Cardbus CIS Pointer, RO Subsystem Device ID, RO Expansion ROM Base Address (not used) Reserved Reserved MAX_LAT, RO 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000
Legend for PCI Configuration Space Table 0x00 or 0x0000 RO CS RW Hardwired to zero Read-only: may be initialized by EEPROM across I2C-compatible serial interface Control and status register Read/write
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CY7C09449PV-AC
Vendor ID Address: 0x01 - 0x00 Default Value: 0x12BE Read-only: Can be initialized from the external memory accessed via the I2C-compatible serial interface This 2-byte register contains the Vendor ID assigned by the PCI SIG. The default value is the Cypress Semiconductor Vendor ID. Using the I2C-compatible serial interface for initialization provides a method to allow a manufacturer to load their own vendor ID. Device ID Address: 0x03 - 0x02 Default Value: 0x3042 Read-only: Can be initialized from the external memory accessed via the I2C-compatible serial interface This 2-byte register contains the device ID assigned by the manufacturer. The default value is the CY7C09449PV chip device ID. Using the I2C-compatible serial interface for initialization provides a method to allow a manufacturer to load their own device ID. Command Address: 0x05 - 0x04 Default Value: 0x0000 Read/Write This 2-byte register contains bits for device control. These bits are normally set by the system BIOS. The following bits are supported: Bit 0: Enable response to I/O space accesses. Bit 1: Enable response to Memory space accesses. Bit 2: Enable PCI bus master operation (may be initialized over the I2C-compatible serial interface). Bit 3: Enable special cycle monitoring, (but CY7C09449PV performs no special function as a target). Bit 4: Enable bus master use of the Memory Write and Invalidate command. Bit 6: Enable the PERR signal for host notification of data parity errors. Bit 8: Enable the SERR signal for host notification of system errors. Bit 9: Enable fast back-to-back transactions to different agents (but CY7C09449PV does not generate). Status Address: 0x07 - 0x06 Default Value: 0x0280 Read-only and Write-1-to-Clear except as indicated. This 2-byte register contains bits for device status. The following bits are supported: Bit 7: Read-only bit set to indicate, as a target, the chip can accept fast back-to-back transactions. Bit 8: Set when PERR is asserted. Bits 10 and 9: Read-only bits set to 0x1 indicating medium response timing for DEVSEL. Bit 12: Set when, as a master, the chip's transaction has been terminated with Target-Abort. Bit 13: Set when, as a master, the chip terminates a transaction with Master-Abort. Bit 14: Set when SERR is asserted. Bit 15: Set whenever a parity error is detected. Revision ID Address: 0x08 Default Value: 0x02 Read-only: Can be initialized from the external memory accessed via the I2C-compatible serial interface. This 1-byte register contains the Revision ID assigned by the manufacturer. The default value is set by Cypress Semiconductor at manufacturing time. Using the I2C-compatible serial interface for initialization provides a method to allow a manufacturer to load their own Revision ID. Class Code Address: 0x0B - 0x09 Default Value: 0x0E0001 Read-only: Can be initialized from the external memory accessed via the I2C-compatible serial interface. This 3-byte register contains the class code assigned by the manufacturer. The default value indicates an I2O base class (0x0E), a sub-class of 0x00, and the programming interface that supports system interrupt capability (0x01). Using the I2Ccompatible serial interface for initialization provides a method to allow a manufacturer to load their own class code. Cache Line Size Address: 0x0C Default Value: 0x00 Read/Write This register contains the cache line size in DWORDs. The only valid size is 0x08; any other value written will result in a 0x00 being written to the register. The value in this register is used to control when the master can perform Memory Write and Invalidate cycles. Additionally, the type of memory read command is determined by this value; (i.e., Memory Read, Memory Read Line, or Memory Read Multiple). Latency Timer Address: 0x0D Default Value: 0x00 Read/Write This register controls how quickly the master must get off the bus if GNT is removed. The CY7C09449PV implements bits [7:3] of this register, providing a granularity of eight clocks. Base Address Register 0 (Memory Type Access) Address: 0x13 - 0x10 Default Value: 0x00000000 Read all 32 bits, Write bits [31-15] Document #: 38-06061 Rev. *A Page 10 of 50
CY7C09449PV-AC
This register provides the base address of the CY7C09449PV memory map. Bits [31-15] are read/write, indicating to the system BIOS that the shared memory space is 32 K bytes. If a PCI memory transaction has address bits [31-15] matching the contents of this register and memory accesses are enabled (by Command register bit 1), then the CY7C09449PV chip will acknowledge and accept the transfer. Base Address Register 1 (I/O Type Access) Address: 0x17 - 0x14 Default Value: 0x00000001 Read all 32 bits, Write bits [31-3] This register provides the base address of the CY7C09449PV I/O pointer space. Bits [31-3] are read/write, indicating to the system BIOS that the I/O pointer space is 8 bytes. If a PCI I/O transaction has address bits [31-3] matching the contents of this and I/O accesses are enabled (by Command register bit 0), then the CY7C09449PV will acknowledge and accept the transfer. Cardbus CIS Pointer Address - 0x2B - 0x28 Default Value: 0x00000000 Read-only: Can be initialized from the external memory accessed via the I2C-compatible serial interface. This register contains the Cardbus Card Information Structure (CIS). Using the I2C-compatible serial interface for initialization provides a method to allow a manufacturer to load their own CIS pointer value. Subsystem Vendor ID Address: 0x2D - 0x2C Default Value: 0x0000 Read-only: Can be initialized from the external memory accessed via the I2C-compatible serial interface. This 2-byte register contains the subsystem vendor ID chosen by the manufacturer. Using the I2C-compatible serial interface for initialization provides a method to allow a manufacturer to load their own subsystem vendor ID. Subsystem Device ID Address: 0x2F - 0x2E Default Value: 0x0000 Read-only: Can be initialized from the external memory accessed via the I2C-compatible serial interface. This 2-byte register contains the subsystem device ID chosen by the manufacturer. Using the I2C-compatible serial interface for initialization provides a method to allow a manufacturer to load their own subsystem device ID. Interrupt Line Address: 0x3C Default Value: 0x00 Read/Write This single-byte register contains the interrupt line routing. Interrupt Pin Address: 0x3D Default Value: 0x00 Read-only: Can be initialized from the external memory accessed via the I2C-compatible serial interface. This single-byte register contains the interrupt pin information. The default value indicates that the CY7C09449PV chip is not connected to the interrupts on the PCI bus. Using the I2Ccompatible serial interface for initialization provides a method to allow a manufacturer to specify which interrupt pin is on the bus. Only bits [2-0] are implemented. All four Interrupt numbers are supported, (INTA through INTD). MIN_GNT Address: 0x3E Default Value: 0x00 Read-only: Can be initialized from the external memory accessed via the I2C-compatible serial interface. This single-byte register contains the minimum grant time in 1/ 4 microsecond increments needed for efficient operation. The default value indicates the add-in card has no major requirements for the setting of the latency timer. The latency timer governs how long a burst transaction may use the PCI bus. Whatever the value, the CY7C09449PV itself does not use the MIN_GNT data. It is used as a means to communicate system requirements to the host. Using the I2C-compatible serial interface for initialization provides a method to allow a manufacturer to load their own minimum grant time reflective of their add-in card requirements. MAX_LAT Address: 0x3F Default Value: 0x00 Read-only: Can be initialized from the external memory accessed via the I2C-compatible serial interface. This single-byte register contains the minimum latency time in 1/4 microsecond increments needed for efficient operation. The default value indicates the add-in card has no major requirements for how soon it needs access to the PCI bus once it has requested an access. Whatever the value, the CY7C09449PV itself does not use MAX_LAT data. It is used as a means to communicate system requirements to the host. Using the I2C-compatible serial interface for initialization provides a method to allow a manufacturer to load their own minimum latency time reflective of their add-in card requirements. PCI Bus Commands All Memory and I/O commands are supported as target and master. * I/O Read C/BE[3:0] = 0x2 * I/O Write C/BE[3:0] = 0x3 * Memory Read C/BE[3:0] = 0x6 * Memory Write C/BE[3:0] = 0x7 * Memory Read Multiple C/BE[3:0] = 0xC * Memory Read Line C/BE[3:0] = 0xE * Memory Write and Invalidate C/BE[3:0] = 0xF All Configuration commands are supported as target and master. Additionally, the CY7C09449PV can perform these acDocument #: 38-06061 Rev. *A Page 11 of 50
CY7C09449PV-AC
cesses on its own PCI Configuration space. Control originates from the Local bus using the CY7C09449PV Direct Access feature. This is a necessary feature for the CY7C09449PV to perform as a Host Bridge device. Type 0 and Type 1 PCI configuration commands may be generated by the CY7C09449PV. For details, see the Direct Access and Host Bridge descriptions in the CY7C09449PV Operations section. * Configuration Read C/BE[3:0] = 0xA * Configuration Write C/BE[3:0] = 0xB Interrupt Acknowledge and Special Cycle are supported on master cycles. As a target, no action is performed by the CY7C09449PV. * Interrupt AcknowledgeC/BE[3:0] = 0x0 * Special Cycle C/BE[3:0] = 0x1 The following command is not supported, a target access will result in no response by the CY7C09449PV as per the PCI specification. * Dual-Address Cycle C/BE[3:0] = 0xD The following commands are PCI Reserved and are not responded to as per PCI specification. * Reserved C/BE[3:0] = 0x4 * Reserved C/BE[3:0] = 0x5 * Reserved C/BE[3:0] = 0x8 * Reserved C/BE[3:0] = 0x9 PCI I/O Pointers Utilization of PCI I/O access is not generally recommended by the PCI special interest group. New system designs should use the PCI Memory access rather than PCI I/O access. In general, this is provided as a support to legacy systems. The CY7C09449PV Base Address Register 1 (BAR1) is the offset reference for PCI I/O access to this device. I/O Address Pointer Address: 0x1 - 0x0 Default Value: unknown, not initialized Write-only The value written to this location is the offset into the CY7C09449PV Memory Map. Bit 15 is "don't care." I/O Data Pointer Address: 0x7 - 0x4 Default Value: unknown, not initialized Read/Write Upon a write to the pointer, the data shall be written to the location in the CY7C09449PV Memory Map specified by the contents of the I/O address pointer. If an I/O read access to the pointer, then the data at the location in the CY7C09449PV Memory Map which is specified by the contents of the I/O address pointer shall be returned. clock, a derivative, or an independent clock source. To run the local interface at PCI clock speeds, any one of the PCLKOUT[2:0] pins should be connected to CLKIN. The basic local processor bus transaction consists of an address phase, followed by one or more data phases. The interface signals are generally divided into those signals that qualify the address phase (ALE, STROBE, SELECT, READ, WRITE, and ADR[14:2]), and those that qualify data phases, (RDY_IN, RDY_IN, BLAST, BE[3:0], and DQ[31:0]). The CY7C09449PV drives RDY_OUT to signal the need for wait states on the local processor bus as well as an indication of valid data on DQ[31:0] during read access of the CY7C09449PV. Note that several of the CY7C09449PV local bus signals have configurable polarity. These are: ALE, BLAST, RDY_OUT, and STROBE. Also, the READ and WRITE signals have special combined signal modes. The basic local-bus cycle starts with the address phase. The address phase is defined as both STROBE and SELECT active at the rising edge of CLKIN. Also sampled at this time are the READ and WRITE signals to determine if the access is a read or write. If the access is a read, then the CY7C09449PV will begin driving the DQ bus at the next CLKIN rising edge. There are two ways to get an address into the CY7C09449PV. With ALE tied active, the address is latched during the address phase. That is, when STROBE and SELECT are active, the address on the ADR[14:2] pins is latched on the rising edge of CLKIN. The second way is to use the trailing edge of ALE to latch the address. The CY7C09449PV still needs a valid address phase (STROBE and SELECT active at the rising edge of CLKIN) before it will begin processing the address. A valid and stable address must occur before the trailing edge of ALE and before the rising edge of CLKIN where STROBE and SELECT are active. After the address phase come wait states and data phases. The STROBE signal can be active or inactive during wait and data phases. A data phase occurs when the RDY_IN and RDY_IN inputs and the RDY_OUT output are all active at the rising edge of CLKIN. If any ready signal is inactive, then the next clock cycle is a wait state. The BE[3:0] pins are sampled during the data phase of write cycles to determine which data bytes are to be written. The data on the DQ pins is also latched at this time. The BLAST signal is sampled during the data phase to determine if the last data phase is occurring. In one mode, an inactive level during the data phase indicates that there are more data phases in the transaction and that the address that was captured in the address phase should be updated. When BLAST is active during the data phase, it indicates that this is the last data phase of the transaction. In the other mode, BLAST is active during every data phase and goes inactive at the end of the last data phase. In both cases, if the access is a read, then the CY7C09449PV will stop driving the DQ bus synchronously with the rising edge of CLKIN for that data phase. Interface Definitions 8-Bit Interface The 8-bit interface option is selected by setting bits BW[1:0] = '00' in the Local Bus Configuration Register. Only data lines DQ[7:0] are used. The unused portion of the data bus, DQ[31:8] must be tied HIGH or LOW; the bits cannot be left Page 12 of 50
Local Bus
General Description The CY7C09449PV provides a configurable local processor bus interface which can provide direct connection to several processor types. The interface is synchronous to the CLKIN signal. The CLKIN signal can be tied to the local processor's Document #: 38-06061 Rev. *A
CY7C09449PV-AC
floating. The least two significant bits of the local address bus should be connected to the byte enable pins BE[3:2]. BE[0] should be tied to RDY_IN which is connected normally. Connect * BE[3] = A1 * BE[2] = A0 * BE[1] = Logic HIGH * BE[0] = Tie to RDY_IN A1, A0 (BE[3], BE[2]) 00 01 10 11 DQ [7:0] Accessed Data Data[7:0] Data[15:8] Data[23:16] Data[31:24] Connect * BE[3] = A1 * BE[2] = Not used, should be tied HIGH * BE[1] = BE1, UDS, BHE (Byte Enable 1, Upper Data Strobe, Byte High Enable) * BE[0] = BE0, LDS, DEN (Byte Enable 0, Lower Data Strobe, Data Enable, A0) A1 (BE[3 ]) 0 1 DQ [15:0] Bus Accessed Data CY7C09449PV Data[15:0] CY7C09449PV Data[31:16]
BW[1:0 ] 01 01 Notes:
BEMODE 0 0
BW[1:0] 00 00 00 00
BEMODE X X X X
16-Bit Interface The 16-bit interface option is selected by setting bits BW[1:0] = '01' in the Local Bus Configuration Register. Only data lines DQ[15:0] are used. The unused portion of the data bus, DQ[31:16] must be tied HIGH or LOW; the bits cannot be left floating. There are two basic modes for 16-bit operation. One is for Motorola-style encoded byte enables and the other is for direct byte enables. This is configured with the Byte Enable mode bit, BEMODE. There is an exception to the data bus wiring for Motorola-style buses if a 32-bit processor bus is configured to only use 16 data bits. The upper 16 bits of the processor bus are connected rather than the lower 16 bits. See the description for BEMODE='1' below. BEMODE = '0' is for operation of other than Motorola-style byte enables. The table below shows where data on the 16-bit bus is routed within the CY7C09449PV internal data structures.
BE[1:0] are used as byte enables. If the processor always does 16-bit accesses, then these can be tied active LOW. These byte enables can also be used for Upper Data Strobe (UDS) and Lower Data Strobe (LDS) for processors which produce these signals. The least significant bit of the local address bus is tied to BE[3], and it must be valid during the address phase. This input must be incremented (toggled) at the end of each data phase. Bursts to the 16-bit interface do not need to start on a DWORD boundary. The internal DWORD address will automatically increment after a data phase where BE[3] is HIGH. BEMODE = '1' is for operation of Motorola-style byte enables. The tables below show where data on the 16-bit bus is placed in the CY7C09449PV internal data structures. For the case where a 32-bit Motorola processor bus is to be configured for 16-bit bus operation, then connect the processor D[31:16] to CY7C09449PV DQ[15:0]. For instance, the Motorola 68360 processor may be operated in this mode. The tables show this mode of operation.
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CY7C09449PV-AC
Connect for encoded byte enables * BE[3] = SIZ1 (Operand Transfer Size, bit 1) * BE[2] = SIZ0 (Operand Transfer Size, bit 0) * BE[1] = A1 * BE[0] = A0 CY7C09449PV External BE[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 BW[1:0] 01 BEMODE 1 Interpretation Use the following table
Interpretation -- 'byte' terminology here uses byte 3 as least significant byte of the processor's internal 32-bit data structure; the signals show pins on the processor. all-byte write starting at byte 0 (D[31:16]) (truncated to two bytes) all-byte write starting at byte 1 (D[23:16]) (truncated to one byte) all-byte write starting at byte 2 (D[31:16]) (truncated to two bytes) all-byte write starting at byte 3 (D[23:16]) (truncated to one byte) single-byte write starting at byte 0 (D[31:24]) single-byte write starting at byte 1 (D[23:16]) single-byte write starting at byte 2 (D[31:24]) single-byte write starting at byte 3 (D[23:16]) two-byte write starting at byte 0 (D[31:16]) two-byte write starting at byte 1 (D[23:16]) (truncated to one byte) two-byte write starting at byte 2 (D[31:16]) two-byte write starting at byte 3 (D[23:16]) (truncated to one byte) three-byte write starting at byte 1 (D[23:16]) (truncated to one byte) three-byte write starting at byte 3 (D[31:24]) (truncated to one byte) three-byte read starting at byte 3 (D[23:16]) (truncated to one byte)
CY7C09449PV Internal BE[3:0] for writes 0011 1011 1100 1110 0111 1011 1101 1110 0011 1011 1100 1110 1011 1110
three-byte write starting at byte 0 (D[31:16]) (truncated to two bytes) 0011 three-byte write starting at byte 2 (D[31:16]) (truncated to two bytes) 1100
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CY7C09449PV-AC
32-Bit Interface The 32-bit interface option is selected by setting bits BW[1:0] = '10' or BW[1:0] = '11' in the Local Bus Configuration Register. Data lines DQ[31:0] are used. With BW[1:0] = '10', the byte enables are used directly as byte write enables. With BW[1:0] = '11', however, the meaning of the byte enables is determined from the following tables (based on BEMODE). For 32-bit processor bus interfaces like the Motorola 68020 or 68030, BW = '11' and BEMODE = '0' settings are used. This supports a special style of using byte addressing instead of fully decoded byte enables. The SIZ1 and SIZ0 signals of the 68020 are connected to the BE[3] and BE[2] pins, respectively, CY7C09449PV External BE[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 and the A1 and A0 signals are connected to the BE[1] and BE[0] pins on the CY7C09449PV. Connect for encoded byte enables * BE[3] = SIZ1 (Operand Transfer Size, bit 1) * BE[2] = SIZ0 (Operand Transfer Size, bit 0) * BE[1] = A1 * BE[0] = A0 BW[1:0] 10 11 BEMODE X 0 Interpretation Use byte enables for all 4 byte lanes Use the following table CY7C09449PV Internal BE[3:0] for writes 0000 1000 1100 1110 0111 1011 1101 1110 0011 1001 1100 1110 0001 1000 1100 1110
Interpretation -- 'byte' terminology here uses byte 3 as least significant byte of the processor's internal 32-bit data structure; the signals show pins on the processor all-byte write starting at byte 0 (D[31:0]) all-byte write starting at byte 1 (D[23:0]) (truncated to three bytes) all-byte write starting at byte 2 (D[15:0]) (truncated to two bytes) all-byte write starting at byte 3 (D[7:0]) (truncated to one byte) single-byte write starting at byte 0 (D[31:24]) single-byte write starting at byte 1 (D[23:16]) single-byte write starting at byte 2 (D[15:8]) single-byte write starting at byte 3 (D[7:0]) two-byte write starting at byte 0 (D[31:16]) two-byte write starting at byte 1 (D[23:8]) two-byte write starting at byte 2 (D[15:0]) two-byte write starting at byte 3 (D[7:0]) (truncated to one byte) three-byte write starting at byte 0 (D[31:8]) three-byte write starting at byte 1 (D[23:0]) three-byte write starting at byte 2 (D[15:0]) (truncated to two bytes) three-byte write starting at byte 3 (D[7:0]) (truncated to one byte)
For 32-bit processor bus interfaces like the Motorola 68040, BW = '11' and BEMODE = '1' settings are used. This supports a special style of using byte addressing instead of fully decoded byte enables. The SIZ1 and SIZ0 signals of the 68040 are connected to the BE[3] and BE[2] pins, respectively, and the A1 and A0 signals are connected to the BE[1] and BE[0] pins on the CY7C09449PV. A cache-line fill is triggered using the SIZ1 and SIZ0 pins on the 68040-type bus. When these bits
are set to '11', the CY7C09449PV will interpret this as a burstof-four, ignoring the burst last signal BLAST. BW[1:0] 11 BEMODE 1 Interpretation Use the following table
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CY7C09449PV-AC
CY7C09449PV External BE[3:0] 00xx 0100 0101 0110 0111 100x 101x 11xx
[1]
Interpretation -- the signals show pins on the processor 32-bit write D[31:0] 8-bit write D[31:24] 8-bit write D[23:16] 8-bit write D[15:8] 8-bit write D[7:0] 16-bit write D[31:16] 16-bit write D[15:0] burst of four 32-bit writes, BLAST not used
CY7C09449PV Internal BE[3:0] for writes 0000 0111 1011 1101 1110 0011 1100 0000
Timing Diagrams
Write Cycle A basic write cycle is illustrated below. It includes a burst of three data phases on a 32-bit wide bus.
BASIC WRITE CYCLE (Burst of Three)
RWMODE = '00', ASMODE = '00', BW = '10', DDOUT = '0'
A W1 W2 W3 D1
A = Address Phase D = Data Phase W = Wait State
W
D2 W
W D2
D3
CLKIN ALE STROBE SELECT# READ# WRITE# (not used) RDY_IN# RDY_IN RDY_OUT# BLAST ADR[14:2] BE#[3:0] DQ[31:0]
BOLD indicates output from PCI-DP
Valid Valid Valid Valid Valid Valid Valid
WAV1A.VSD 9/11/9
Note: 1. This encoding, {BW[1:0], BEMODE, BE[3:2]} = {'11111'}, results in a burst of four DWORD. BLAST should remain active.
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CY7C09449PV-AC
Read Cycle The basic read cycle differs from the write cycle only in the level of the READ and WRITE signals, and the timing and driving of the data bus DQ. A basic read burst of four data phases on a 32-bit wide bus is illustrated.
BASIC READ CYCLE (Burst of Four) RWMODE='00', ASMODE='00', BW='10', DDOUT = '0'
A W1 W2 D1
A = Address Phase D = Data Phase W = Wait State
D2 W D3 W D4
CLKIN ALE STROBE SELECT# READ# WRITE# (not used) RDY_IN# RDY_IN RDY_OUT#
BLAST# ADR[14:2] BE#[3:0] DQ[31:0]
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
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CY7C09449PV-AC
Basic 8-bit Interface The following two waveforms illustrate the operation of the 8bit interface mode. Note that only data lines DQ[7:0] are used. DQ[31:8] are unused and must be tied high or low; they cannot be left floating. The least significant bits of the local address, A[1] and A[0], must be connected to the byte enable pins BE[3] and BE[2], respectively. These must be valid during the address phase.
Single Data Read
CLKIN
In burst operation, BE#[3:2] are inputs used at A1 and A0 of the local address bus. Bursts to the 8-bit interface do not need to start on a DWORD boundary. The internal DWORD address will automatically increment after a data phase where BE[3:2] equals '11', (A[1:0] = '11'). The first waveform illustrates single cycle operation and the second illustrates data burst operation.
ASMODE= '00', RWMODE= '00', BW =' 00', DDOUT = '0 Single Data Write
~ ~ ~ ~ ~ ~ ~ ~ ~
Valid
STROBE
SELECT#
READ#
WRITE# (not used) RDY_IN# RDY_IN
RDY_OUT# BLAST#
ADR[14:2]
~ ~ ~ ~
DATA OUT
Valid
BE#[3:2]
Valid
Valid
BE#[1]
(high) (not used)
BE#[0]
DQ[7:0] BOLD indicates output from PCI-DP
~
DATA IN
PCI-DP drives DQ bus here
}
WAV6A.VSD 9/11/9
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CY7C09449PV-AC
ASMODE = '00', RWMODE = '00', BW = '00', DDOUT = '0'
CLKIN
STROBE
SELECT#
READ#
WRITE# (not used) RDY_IN#
RDY_IN
RDY_OUT# BLAST#
ADR[14:2]
Valid
BE#[3:2]
00 Valid
01
10
11
00
BE#[1]
(high)
BE#[0] (not used) DQ[7:0]
Data1 Data2 Data3 Data4
BOLD indicates output from PCI-DP
PCI-DP drives DQ bus here
Internal DWORD address incremented her
WAV6B.VSD 9/11/98
Basic 16-bit Interface The following two waveforms illustrate the operation of the 16bit interface mode. Note that only data lines DQ[15:0] are used. DQ[31:16] are unused and must be tied HIGH or LOW; they cannot be left floating. The least significant bit of the local address of the 16-bit bus, A[1], must be connected to the byte enable pin BE[3]. It must be valid during the address phase. Note that BE[1:0] are used as byte enables. If the processor always does 16-bit accesses, then these can be tied active LOW. These byte enables can also be used for Upper Data
Strobe (UDS) and Lower Data Strobe (LDS) for processors which produce these signals. In burst operation, BE[3] must be incremented (toggled) at the end of each data phase. Bursts to the 16-bit interface do not need to start on a DWORD boundary. The internal DWORD address will automatically increment after a data phase where BE[3] equals '1', (A[1] = '1'). The first waveform illustrates single cycle operation and the second illustrates data burst operation.
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CY7C09449PV-AC
ASMODE = = '00', RWMODE BW = `01', DDOUT `0' ASMODE `00', RWMODE = `00',= '00', BW = '00',=DDOUT = '0'
Single Data Read
CLKIN
Single Data Write
~ ~ ~ ~ ~ ~ ~ ~ ~
Valid Valid
STROBE
SELECT#
READ#
WRITE# (not used) RDY_IN# RDY_IN
RDY_OUT#
BLAST#
ADR[14:2]
BE#[3]
~ ~ ~ ~
DATA OUT
Valid Valid
BE#[2] (not used) BE#[1:0]
DQ[15:0] BOLD indicates output from PCI-DP
~
DATA IN
PCI-DP drives DQ bus here
}
WAV7A.VSD 9/11/9
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CY7C09449PV-AC
ASMODE = '00', RWMODE = '00', BW = '01', DDOUT = '0'
CLKIN
STROBE
SELECT#
READ#
W RITE# (not used) RDY_IN# RDY_IN
RDY_OUT#
BLAST#
ADR[14:2]
Valid
BE#[3]
Valid
0
1
0
1
BE#[2] (not used) BE#[1:0]
DQ[15:0]
Data0 Data1
Data2 Data3
BOLD indicates output from PCI-DP
PCI-DP drives DQ bus here
WAV7B.VSD 9/11/98
ALE--Address Latch Enable The ALE signal may be used in two modes. With ALE tied active, the address is latched during the address phase. That is, when the STROBE and SELECT signals are active, the address on the ADR[14:2] pins is latched on the rising edge of CLKIN. The second way is to use the trailing edge of ALE to latch the address. The CY7C09449PV still needs a valid adCycle Start CLKIN
dress phase (STROBE and SELECT active at the rising edge of CLKIN) before it will begin processing the address. A valid and stable address must occur before the trailing edge of ALE and before the rising edge of CLKIN where STROBE and SELECT are active. The active polarity of ALE is defined in the Operations Registers: ALE_POL of the Local Bus Configuration Register.
Cycle Start
ALE
STROBE
SELECT#
ADR[14:2]
Valid
Valid
Address set-up time with respect to rising edge of CLKIN
Address set-up time with respect to falling edge of ALE
ALE.VSD 9/11/9
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CY7C09449PV-AC
RDY_OUT_OE--Ready Out Three-state Mode The RDY_OUT signal may be configured to drive at all times or to three-state when inactive. The three-state mode is a sustained deasserted function. In three-state mode, when RDY_OUT is to go inactive, RDY_OUT is driven to the deasserted level for one clock, and then three-stated. It remains three-stated until RDY_OUT is to be asserted. The logic polarity of RDY_OUT is programmable. The mode (RDY_OUT_OE) and polarity (RDYOUT_POL) controls are set in the Local Bus Configuration Register, LBUSCFG, of the Operations Registers. DDOUT--Delayed Data Out The delayed data out control defines when the CY7C09449PV drives the DQ bus during a local bus read. The control is defined in the Operations Registers: DDOUT of the Local Bus Configuration Register. When DDOUT = '0', the CY7C09449PV will drive the DQ bus during a read starting one clock after the address phase and stop driving at the clock edge where both of the ready inputs and BLAST# are active. When DDOUT = '1', the CY7C09449PV will drive the DQ bus during a read starting one CLKIN clock after the address phase and stop driving one clock after the clock edge where the two ready inputs and BLAST are active. The data is driven for one clock period after the signal that the transaction is over. In the case of multiple data phases, it adds one clock cycle to the starting latency of the burst.
A = Address Phase D = Data Phase W = Wait State D
READ CYCLE with DDOUT=1
RWMODE='00', ASMODE='00', BW='10', DDOUT='1' A CLKIN W1 W2
ALE
STROBE
SELECT#
READ#
WRITE# (not used) RDY_IN#
RDY_IN
RDY_OUT#
BLAST#
ADR[14:2]
Valid Valid Valid
BE#[3:0]
DQ[31:0] BOLD indicates output from PCI-DP
Data Output is extended for an extra cycle
EDOUT.VSD 9/11/9
RDY_OUT--Ready Out STROBE can be active or inactive during data phases. However, if STROBE is active during the data phase when BLAST is active AND the extended ready out control (XTND_RDY_OUT) is set, the CY7C09449PV keeps RDY_OUT active until STROBE goes inactive. In the case of a read, the CY7C09449PV will continue to drive the data on DQ until STROBE is deasserted.
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CY7C09449PV-AC
Normal RDY_OUT#
CLKIN
Extended RDY_OUT#
STROBE
RDY_IN#
RDY_IN
BLAST#
RDY_OUT#
When STROBE is inactive at the last data phase, RDY_OUT# goes inactive at the next CLKIN edge.
When STROBEACTIVE the last data is at phase, RDY_OUT# goes inactive after STROBE goes inactive.
RDYOUT#.VSD 9/11/
LINE_WRAP_DIS--Cache Line Wrap Disable This setting is used to disable cache line wrapping, LINE_WRAP_DIS = `1'. Cache line wrapping only occurs when the local bus interface is set for 32 bit width with encoded byte enables, using the Motorola byte enable encoding, and the bus SIZ bits indicate a cache line access. Specifically, this is when BW = '11', BEMODE = '0', and BE[3] = BE[2] = `1.' If a cache line access is made and cache line wrapping is disabled, then the burst will proceed linearly with no implicit address wraparound at the 4 DWORD boundary. ASMODE--Address Strobe Mode The address strobe mode control defines the polarity and the timing used to sample the CY7C09449PV address strobe input signal, STROBE. The two-bit control field is defined in the Operations Registers: ASMODE of the Local Bus Configuration Register.
ASMODE[0] defines the polarity of the STROBE input signal; '0' = active LOW and '1' = active HIGH. ASMODE[1] controls the sampling edge of the STROBE signal. Logic LOW indicates that the signal is sampled using the rising edge of CLKIN. A logic HIGH indicates that the signal is sampled with the falling edge of CLKIN. Sampling on the falling edge should only be used when the required minimum setup time with respect to the clock rising edge cannot be met on the signals. The following waveform illustrates the operation of the ASMODE[1] pin. ADR and READ are sampled at E2, and a valid write occurs at E4. Note that STROBE is captured at the negative edge labeled NE1 and that the ADR and READ signals are sampled at the positive clock edge labeled E2. Also note that the ready signals are sampled at the negative edge labeled NE4 and not at the positive edge labeled E5. STROBE is active LOW since ASMODE[0] = '0.'
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ASMODE[1]='1' (32-bit write, single data phase) RWMODE='00', ASMODE='10', BW='10', DDOUT = '0' ASMODE[1] = '1'
E0 E1 E2 E3 E4 E5
CLKIN STROBE SELECT# READ# WRITE# RDY_IN# RDY_IN RDY_OUT# BLAST# ADR[14:2] BE#[3:0] DQ#[31:0] BOLD indicates output from PCI-DP
Valid
NE4 NE1
Valid
Valid
WAV3B.VSD 9/11/98
Falling Edge Sampling for RDY_IN, RDY_IN, SELECT, and STROBE These signals may be configured for falling edge sampling within the Local Bus Configuration Register (LBUSCFG) of the Operations Registers. RDY_IN and RDY_IN sampling is configured by the RDY_IN_FALL bit, SELECT sampling is configured by the SELECT_FALL bit, and STROBE sampling is configured by the ASMODE[1] bit. Setting any one or all of these bits will not effect the sampling of other signals on the local bus. That is, all other signals that are synchronous inputs are sampled on the rising edge of the local bus clock, CLKIN. When a negative edge sample is used, the other signals are qualified by that sample on the immediately following rising edge of CLKIN. For example, study the prior waveform illustrating operation of ASMODE. In that diagram, STROBE is configured to sample on the falling edge of CLKIN because
ASMODE[1]='1'. An active STROBE indicates an address phase. The valid address is captured on the first rising clock edge after STROBE is sampled active. RWMODE--Read Write Mode The read write mode control defines how the address strobe (STROBE), read (READ), and write (WRITE) input signals are interpreted by the CY7C09449PV internal logic. The two-bit control field is defined in the Operations Registers: RWMODE of the Local Bus Configuration Register. Each of the four cases for RWMODE are illustrated in the following four diagrams. Use RWMODE = '00' to interface to a processor that has a read-write signal defined as W_R (write is logic 1, read is logic 0). In this mode, the WRITE is not used and should be tied HIGH. A write cycle is illustrated below.
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RWMODE='00', ASMODE='00', BW='10', DDOUT = '0'
A CLKIN W D
STROBE
SELECT#
READ# WRITE# (not used) RDY_IN#
RDY_IN
RDY_OUT#
BLAST#
ADR[14:2] BE#[3:0]
Valid
Valid
DQ[31:0]
Valid
Use RWMODE = '01' to interface to a processor that has a read-write signal defined at R_W (write is logic 0, read is logic 1). In this mode, the WRITE acts as R_W and it is sampled
Single Data Read
CLKIN
when SELECT and STROBE are both active. The READ pin is not used and should be tied HIGH. This is illustrated below.
RWMODE='01', ASMODE='00', BW='10', DDOUT = '0'
Single Data Write
~ ~ ~ ~ ~ ~ ~ ~ ~
Valid
STROBE
SELECT#
READ# (not used) WRITE# (acts as W# / R) RDY_IN# RDY_IN
RDY_OUT#
BLAST#
ADR[14:2]
~ ~
DATA OUT
Valid
BE#[3:0]
Valid
DQ[31:0] BOLD indicates output from PCI-DP
~
DATA IN
}
PCI-DP drives DQ bus here
WAV5A.VSD 9/11/9
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Use RWMODE = '10' or RWMODE = '11' to interface to a processor that has separate active LOW read and write signals. The two modes are identical. Sampling of the READ and WRITE signals is used as the internal address strobe in place of the STROBE signal. This is illustrated below.
RWMODE='1x', ASMODE='00', BW='10', DDOUT = '0' Single Data Read
CLKIN
Single Data Write
STROBE (not used) SELECT#
~ ~ ~ ~ ~ ~ ~ ~
Valid
READ#
WRITE#
RDY_IN# RDY_IN
RDY_OUT#
BLAST# ADR[14:2]
~ ~
DATA OUT
Valid
BE#[3:0]
DQ[31:0] BOLD indicates output from PCI-DP
~ ~
Valid
DATA IN
PCI-DP drives DQ bus here
}
WAV5B1.VSD 10/14/
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CY7C09449PV-AC
I2C Serial Port and Auto-Configuration
The CY7C09449PV I2C serial port may master the I2C bus, but it is not a target on the bus. Read and write access to the port is available to both the PCI and Local buses via the I2C programming Operations Registers. The CY7C09449PV supports single byte device internal addressing. The port can be used for Auto-Configuration of the CY7C09449PV as well as for basic read and write access to I2C-compatible devices connected to the port. Auto-Configuration is the function that uses the port to load CY7C09449PV configuration information. A typical device containing the data is a serial Electrically Erasable Programmable Read Only Memory (EEPROM). The EEPROM includes data for some PCI configuration registers and some Operations Registers. The EEPROM containing the CY7C09449PV configuration data must be located at I2C device address 0x0 and must contain the proper CY7C09449PV Signature. For details, see the memory map below and the accompanying field descriptions.
I2C Serial Port Device 0x0 Memory Map for Auto-Configuration Byte 3 don't care CY7C09449PV Signature 0x48 Device ID high byte Class Code, base class high byte Subsystem Device ID high byte MAX_LAT Cardbus CIS Pointer high byte reserved reserved reserved reserved reserved reserved don't care CY7C09449PV Signature 0x37 Device ID low byte Class Code, sub-class middle byte Subsystem Device ID low byte MIN_GNT Cardbus CIS Pointer low byte reserved reserved reserved reserved reserved Local Bus Configuration high byte reserved Host Control bits [23:16] don't care Byte 2 Byte 1 don't care reserved Vendor ID high byte Class Code, programming intf. low byte Subsystem Vendor ID high byte Interrupt Pin, Master Enable[2] Cardbus CIS Pointer high byte reserved reserved reserved reserved reserved Local Bus Configuration middle byte reserved Host Control bits [15:8] don't care Byte 0 don't care reserved Vendor ID low byte Revision ID Internal Address, Byte Offset 0x00 ... 0x3F 0x40 0x44 0x48
Subsystem Vendor ID low byte don't care Cardbus CIS Pointer low byte reserved reserved reserved reserved reserved Local Bus Configuration low byte reserved Host Control bits [7:0] don't care
0x4C
0x50 0x54
0x58 0x5C 0x60 0x64 0x68 0x6C
reserved Host Control bits [31:24] don't care
0x70 0x74 0xFF ... 0x78
Notes: 2. Master Enable is the most significant bit of this byte; see text for more description of this flag. 3. The recommended value for reserved data in the EEPROM is `1'
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CY7C09449PV Signature Address: 0x43 - 0x42 Device Configuration Signature: A valid EEPROM CY7C09449PV configuration image is indicated at this address by the value of 0x4837. It is read from the EEPROM at I2C device address 0x0 immediately after the CY7C09449PV comes out of reset. The CY7C09449PV comes out of reset as indicated by the deassertion of the CY7C09449PV RST input. Upon recognition of a valid signature, the contents of the EEPROM will be transferred to the appropriate CY7C09449PV registers. The appropriate registers are indicated by the other labeled fields of the I2C Serial Port Device 0x0 Memory Map for Auto-Configuration and are described in this section. If the value at this location is not 0x4837, then the transfer will not occur and the default (reset) values for the CY7C09449PV registers will remain in effect after the CY7C09449PV comes out of reset. Vendor ID Address: 0x45 - 0x44 PCI Configuration Vendor ID: the meaning of this field is described in the PCI Bus section. Device ID Address: 0x47 - 0x46 PCI Configuration Device ID: the meaning of this field is described in the PCI Bus section. Revision ID Address: 0x48 PCI Configuration Revision ID: the meaning of this field is described in the PCI Bus section. Class Code Address: 0x4B - 0x49 PCI Configuration Class Code (Base Class, Sub-Class, Programming Interface): the meaning of this field is described in the PCI Bus section. Subsystem Vendor ID Address: 0x4D - 0x4C PCI Configuration Subsystem Vendor ID: the meaning of this field is described in the PCI Bus section. Subsystem Device ID Address: 0x4F - 0x4E PCI Configuration Subsystem Device ID: the meaning of this field is described in the PCI Bus section. Interrupt Pin Address: 0x51, bits 2, 1, 0 PCI Configuration Interrupt Pin: the meaning of this field is described in the PCI Bus section. Master Enable Address: 0x51, bit 7 PCI Configuration Command Bit 2: enable PCI bus master operation. For a host bridge, this typically must be set to allow the host to configure itself and configure and access other deDocument #: 38-06061 Rev. *A vices on the PCI bus. Even though an external master can manipulate the PCI Command register, it is typical that the host is the first device to configure devices on the PCI bus. Since the default value for PCI Command bit 2 is that PCI bus mastering is disabled, the Master Enable bit in the EEPROM image should be set to enable PCI mastering. MIN_GNT Address: 0x52 PCI Configuration MIN_GNT: the meaning of this field is described in the PCI Bus section. MAX_LAT Address: 0x53 PCI Configuration MAX_LAT: the meaning of this field is described in the PCI Bus section. Cardbus CIS Pointer Address: 0x57 - 0x54 PCI Configuration Cardbus CIS Pointer: the meaning of this field is described in the PCI Bus section. Local Bus Configuration Address: 0x6C - 0x6E Operations Registers Local Bus Configuration: the detailed meaning of this field is described in the Operations Registers section. For the CY7C09449PV Local bus to exhibit the correct protocol, the Local Bus Configuration Operations Register needs to be loaded before the CY7C09449PV is accessed via the Local bus interface. The Local bus interface circuitry will be held in reset until transfer of the EEPROM configuration data is complete. At such completion, and dependent upon the state of the Host Control Operations Register, the Local bus will be available for access using the programmed Local bus interface protocol. Host Control Address: 0x77 - 0x74 Operations Registers Host Control: Only bits 1 and 0 have meaning; the other bits are reserved. When programming bits 1 and 0, other bits of the DWORD should be written with '0'. One of two reset controls from the CY7C09449PV may be used to reset the local processor system. The CY7C09449PV RSTOUT output signal is a buffered copy of the PCI bus RST signal and is not conditioned by the bits of the Host Control register. This signal will deassert before the Auto-Configuration process completes, so some applications will not use this signal in order to prevent premature local processor attempts to access the CY7C09449PV. The other form of reset control provides a direct link to the Auto-Configuration process. Using this method, the local processor will remain in reset until completion of the Auto-Configuration process. In this case, the CY7C09449PV RSTOUTD output signal (or its active HIGH version, RSTOUTD) is used to reset the local processor. This signal is a copy of bit 0 of the Host Control register (the Local Processor Reset). With AutoConfiguration, the local processor will be either held in reset or released from reset depending upon the value in the EEPROM. Furthermore, as an Operations Register, the Host Control register may be accessed from the PCI bus once AutoConfiguration is complete. Therefore, if it is desired that the Page 28 of 50
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local processor be held in reset until updated by a command over the PCI bus, bit 0 of this field should be set. Bit 1 of the Host Control register should be cleared in most cases. Setting it to '1' will reset the Operations Registers to their default state and thereby reinitialize the Local Bus Configuration register. This bit is typically used only for debug or maintenance operations. Another seldom used operation is setting the Host Control register from the local processor. Even though the Operations Register is available from the Local bus, setting either bit 0 or bit 1 to '1' will lock-out the local processor from accessing the CY7C09449PV by way of the Local bus interface. be provided or one of the CY7C09449PV PCLKOUT[2:0] signal outputs may be used. PCLKOUT is a copy of the PCI Clock input, CLK. The PCLKOUT signals are intended to be an option for the user to connect to other circuits as well. Also available to support other circuits, the user may connect any or all of the three reset outputs from the CY7C09449PV. RSTOUT is a registered copy of the PCI Reset input, RST. It is synchronous to CLKIN. The other two reset output signals, RSTOUTD and RSTOUTD, are the copy of a bit in an Operations Register, the 'R' bit of the Host Control Register. RSTOUTD and RSTOUTD are complements of each other and are synchronous to CLKIN. Upon power-up reset of the CY7C09449PV (via the PCI Reset RST) this bit will be set active. It may be cleared during the start-up process using the I2C serial interface or it may be cleared or set via commands received over the PCI bus. Therefore, these signals may be used to hold a local processor in reset until CY7C09449PV configuration is complete or when a host is ready to release the local processor to begin its operations. Operations Registers Addresses This is a summary table of the CY7C09449PV Operations Registers. Register locations are the offset from the Base Address Register 0 and are DWORD aligned. The value shown is the address of the least significant byte of the register offset. Default, power-up values are also shown. Both numbers are documented in hexadecimal notation. Bit positions in gray are unused and read back as '0' unless otherwise indicated in the default value.
Operations Registers
These registers are the means by which CY7C09449PV functions are accessed. Access is available via either interface, the PCI bus or the Local bus. The Operations Registers include the PCI Bus Mastering registers (DMA), the I2O messaging unit registers, the interrupt registers, the mail boxes, and the direct access register. Also included in the Operations Registers are the initialization and configuration registers used to customize the CY7C09449PV operation to the user's needs. The critical Host Control Register and Local Bus Configuration Register may be programmed during the system initialization process. Programming via the I2C serial is available for this purpose. The Operations Registers reside in the Local bus clock domain, therefore, a clock must be applied to CLKIN for proper operation of the CY7C09449PV. Either an external clock may
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Operations Register 31 24 23 16 15 8 7 I I2O Host Interrupt Mask Register M I2O Local Interrupt Status Register I I2O Local Interrupt Mask Register M I2O FIFO Access Inbound Free FIFO (read only) and Inbound Post FIFO (write only) Outbound Post FIFO (read only) and Outbound Free FIFO (write only) Inbound Post FIFO (read only) and Inbound Free FIFO (write only) Outbound Free FIFO (read only) and Outbound Post FIFO (write only) Direct Access PCI Physical Base Address (4 Gbyte, 8 Kb blocks) I2C Serial Command Register (write only) Device Address Byte 3 Memory Address Byte 2 Write Data Byte 1 Byte 0 ACK DMA Local Base Address Register Local Base Address (16 Kbyte) DMA Host Base Address Register PCI Base Address (4 Gbyte) DMA Burst Size Register DMA Burst Size (16K byte) DMA Control Register LP Arbitration Utility Flag Register
L 3 P 3 L 2 P 2 L 1 P 1 L 0 P 0 PI
Offset / Mnemonic 0 Default Value 0x0030 0x0034 0x0038 0x003C all default as empty FIFO, read as 0xFFFFFFFF 0x0040 0x0044 0x0048 0x0460 F
A1A0 BE for Reads
I2O Host Interrupt Status Register
I2OHISR I2OHIMR I2OLISR I2OLIMR
0x00000000 0xFFFFFFFF 0x00000000 0xFFFFFFFF IBFPFIFO OBPFFIFO IBPFFIFO DAHBASE NVCMD n/A 0x04A4 0x04A8 D NVREAD NVSTAT 0xXXXXXXXX 0x000000XX 0x04B0 DMALBASE 0x0000XXXX 0x04B4 DMAHBASE 0xXXXXXXXX 0x04B8 0x04BC W 0x04C0 DMASIZE DMACTL ARBUTIL 0x0000XXXX 0x0000000X 0x00000000 0x04E0 SR 0x04E4 HCTL HINT HLDATA LINT LHDATA
0x004C OBFPFIFO PCI TR 0xXXXXXXXX 0x04A0
I2C Serial Read Data Register I2C Serial Status Register
Host Control Host Interrupt Control/Status Interrupt Enable Host to Local Data Mailbox I Local Processor Interrupt Control/Status Interrupt Enable Local to Host Data Mailbox I Local Bus Configuration Local Bus Configuration Byte 1 Byte 0 Interrupt Status Byte 1 Byte 0 Interrupt Status
0x00000001 0x00000000 0x04E8 0x04F4 0x04F8 0x0000XXXX 0x00000000 0x0000XXXX 0x04FC LBUSCFG 0x00010B50
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Operations Registers Descriptions Detailed descriptions of the Operations Registers follow. Register locations are the offset from the Base Address Register 0 and are DWORD aligned. The value shown is the address I2O Registers I2O Host Interrupt Status Register - I2OHISR0x0030
31
3 0
of the least significant byte of the register offset. The offsets are documented in hexadecimal notation. Unused bits are grayed-out. Unused bits are read as '0' unless otherwise indicated.
I Bit 3 -- I Description Interrupt from the Outbound Post FIFO--the FIFO is not empty. This bit is continuously updated to reflect the status of the FIFO. It is Read-only; `0': no interrupt; `1': interrupt signalled. '0' default. Note: Unused bits in this register are read as 0s.
I2O Host Interrupt Mask Register - I2OHIMR0x0034
31 3 0
M Bit 3 -- M Description Host Interrupt Mask Bit 1: interrupt is masked (default) 0: interrupt is not masked Note: Unused bits in this register are read as 1s.
I2O Local Interrupt Status Register - I2OLISR0x0038
31 3 0
I Bit 3 -- I Description Interrupt from the Inbound Post FIFO--the FIFO is not empty. This bit is continuously updated to reflect the status of the FIFO. It is Read-only; `0': no interrupt; `1': interrupt signalled. '0' default. Note: Unused bits in this register are read as 0s.
I2O Local Interrupt Mask Register - I2OLIMR0x003C
31 3 0
M Bit 3 -- M Description Local Interrupt Mask Bit 1: interrupt is masked (default) 0: interrupt is not masked Note: Unused bits in this register are read as 1s.
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I2O Inbound Free / Post FIFO - IBFPFIFO0x0040
31 0
Inbound Free FIFO (read only) and Inbound Post FIFO (write only) Bit 31:0 Description A shared port -- Reading from this port returns data from the Inbound Free FIFO. The read of an empty FIFO returns 0xFFFF FFFF. Writing to this port places data into the Inbound Post FIFO. If the FIFO is already full, the contents of the FIFO will not change; the data written will be lost. The FIFO is initially empty. An asserted RST# empties all CY7C09449PV FIFO; all data will be lost.
I2O Outbound Post / Free FIFO - OBPFFIFO0x0044
31 0
Outbound Post FIFO (read only) and Outbound Free FIFO (write only) Bit 31:0 Description A shared port -- Reading from this port returns data from the Outbound Post FIFO. The read of an empty FIFO returns 0xFFFF FFFF. Writing to this port places data into the Outbound Free FIFO. If the FIFO is already full, the contents of the FIFO will not change; the data written will be lost. The FIFO is initially empty. An asserted RST empties all CY7C09449PV FIFO; all data will be lost.
I2O Inbound Post / Free FIFO - IBPFFIFO0x0048
31 0
Inbound Post FIFO (read only) and Inbound Free FIFO (write only) Bit 31:0 Description A shared port -- Reading from this port returns data from the Inbound Post FIFO. The read of an empty FIFO returns 0xFFFF FFFF. Writing to this port places data into the Inbound Free FIFO. If the FIFO is already full, the contents of the FIFO will not change; the data written will be lost. The FIFO is initially empty. An asserted RST empties all CY7C09449PV FIFO; all data will be lost.
I2O Outbound Free / Post FIFO -OBFPFIFO0x004C
31 0
Outbound Free FIFO (read only) and Outbound Post FIFO (write only) Bit 31:0 Description A shared port -- Reading from this port returns data from the Outbound Free FIFO. The read of an empty FIFO returns 0xFFFF FFFF. Writing to this port places data into the Outbound Post FIFO. If the FIFO is already full, the contents of the FIFO will not change; the data written will be lost. The FIFO is initially empty. An asserted RST empties all CY7C09449PV FIFO; all data will be lost.
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Direct Access Register Direct Access Host Physical Base Address Register - DAHBASE0x0460
31 13 11 9 8 7
for Reads
4
2
1
0
PCI Physical Base Address (4G byte, 8K byte blocks)
F
A1A0 Byte Enables
Type
Bit 31:13 11 -- F 9:8 7:4 2:1 Type
Description PCI Physical Base Address specifying 8 Kbyte block When '1', force contents of A1A0 to PCI during the PCI address phase. Value to be placed on PCI bus, PCI A1 = bit 9, PCI A0 = bit 8. Data Byte Enables for PCI Master Reads, C/BE#[3:0]. PCI command cycle type for PCI Master Access 00 = interrupt acknowledge (read) (PCI command 0x0) or special cycle (write) (PCI command 0x1) 01 = I/O cycle (read or write) (PCI command 0x2 or 0x3) 10 = memory cycle (read or write) (PCI command 0x6 or 0x7) 11 = configuration cycle (read or write) (PCI command 0xA or 0xB)
I2C Serial Port Registers I2C Serial Command Register -- NVCMD (a write only register)0x04A0
31 30
24 23 16 15 8 7 1 0
Device Address Bit 30:24 23:16 15:8 1 -- T
Memory Address
Write Data Description
TR
Device Address. Device address of the I2C serial device. Default is 1010000. Memory Address. Address within the I2C serial device. Write Data. Write data. This data is ignored if the command is a read. Read Type. This bit is ignored if the command is a write. The data read from a I2C serial device is accessible from the NVREAD register. 1 = 4-byte read 0 = single-byte read Read / Write 1 = read command 0 = write command Note: The write of this byte triggers the start of the EEPROM access. In an 8- or 16-bit system, this location must be written after the address and data have been written.
0 -- R
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I2C Serial Read Data Register -- NVREAD0x04A4 This register contains one or four bytes of data read from the I2C serial EEPROM.
31 24 23
16 15 8 7 0
Byte 3 Bit 31:24 Byte 3 23:16 Byte 2 15:8 Byte 1 7:0 Byte 0
Byte 2
Byte 1
Byte 0 Description
Stores sequential read, byte 3. Undefined for single byte read. Stores sequential read, byte 2. Undefined for single byte read. Stores sequential read, byte 1. Undefined for single byte read. Stores single read and sequential read, byte 0.
I2C Serial Status Register - NVSTAT0x04A8 This register contains status information about the I2C serial data transfer.
31 8 7 5 4 0
ACK Bit 7:5 -- ACK Description Acknowledge bit 7 = device address ack bit. 0 = ack, 1 = no ack. bit 6 = address ack bit. 0 = ack, 1 = no ack. bit 5 = second address ack bit. 0 = ack, 1 = no ack. In a successful read or write, these bits will be 000. Done Indicator 1 = done 0 = in progress
D
0 -- D
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PCI Bus Mastering (DMA) Registers DMA Local Base Address Register - DMALBASE0x04B0
31 14 13 2 0
Local Base Address (16K byte) Bit 13:2 Description Local Base Address - This is the first address of the DMA in the local memory. This register has DWORD resolution.
DMA Host Physical Base Address Register - DMAHBASE0x04B4
31 2 0
PCI Physical Base Address (4 Gbyte) Bit 31:2 Description PCI Physical Base Address - This is the first address of the DMA in the host's memory space. This register has DWORD resolution. 0x04B8
14 13 2 0
DMA Size Register - DMASIZE
31
DMA Burst Size (16K byte) Bit 13:2 Description Burst Size for any mastered DMA, read or write. This register has DWORD resolution.
DMA Control Register - DMACTL0x04BC
31 10 9 8 7 2 1
PI
0
LP Bit 9 -- L Description
W
Local Ownership: Writing to this bit by the local processor will update the value if and only if the P bit is not set to `1.' A write to this bit from the PCI bus will never update this bit. This bit (along with the P bit) is intended to facilitate software arbitration of the DMA registers. '0' default. PCI Ownership: Writing to this bit by the PCI bus will update the value if and only if the L bit is not set to `1'. A write to this bit from the local processor will never update this bit. This bit (along with the L bit) is intended to facilitate software arbitration of the DMA registers. '0' default. Pre-Fetch Inhibit for PCI memory reads: When this bit is set to one, the CY7C09449PV PCI bus master engine will only use the PCI Read command (0x6). When this bit is zero (default), the CY7C09449PV PCI bus master engine will use PCI commands Read (0x6), Read Line (0xC), and Read Multiple (0xE) as appropriate to optimize utilization of the PCI system bus(es). Write: Determines the direction of the DMA and starts transfer. 1: DMA operation is a write to the PCI bus memory from the CY7C09449PV shared memory. 0: DMA operation is a read from the PCI bus memory into the CY7C09449PV shared memory. A write to the low byte of this register triggers the DMA to occur. '0' default.
8 -- P
1 -- PI
0 -- W
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Arbitration Utility Flag Register - ARB_FLAGS0x04C0
31 25 24 23
L3 P3
18
17 16 15
L2 P2
10 9
8
7
2
1
0
L1 P1
L0 P0
Bit 25 -- L3 24 -- P3 17 -- L2 16 --P2 9 -- L1 8 -- P1 1 -- L0 0 -- P0
Description L3 Ownership: A write to this bit by the local processor will update this bit if and only if the P3 bit is not set to `1'. '0' default. P3 Ownership: A write to this bit by the PCI bus will update this bit if and only if the L3 bit is not set. '0' default. L2 Ownership: A write to this bit by the local processor will update this bit if and only if the P2 bit is not set to `1'. '0' default. P2 Ownership: A write to this bit by the PCI bus will update this bit if and only if the L2 bit is not set. '0' default. L1 Ownership: A write to this bit by the local processor will update this bit if and only if the P1 bit is not set to `1'. '0' default. P1 Ownership: A write to this bit by the PCI bus will update this bit if and only if the L1 bit is not set. '0' default. L0 Ownership: A write to this bit by the local processor will update this bit if and only if the P0 bit is not set to `1'. '0' default. P0 Ownership: A write to this bit by the PCI bus will update this bit if and only if the L0 bit is not set. '0' default.
Host Control and Status Registers Host Control Register - HCTL0x04E0
31 2 1 0
SR
Bit 1 -- S
Description Soft Reset - This bit controls the internal reset for the CY7C09449PV. 1 = reset active 0 = not reset (default) Local Processor Reset - This bit controls the RSTOUTD and RSTOUTD pins. 1 = reset active (default state, RSTOUTD pin is LOW, RSTOUTD pin is HIGH) 0 = not reset (RSTOUTD pin is HIGH, RSTOUTD pin is LOW) erations during product development. When S = `1,' it will reset all of the Operations Registers according to their reset default values with the following exceptions: * DMACTL (at offset 0x04BC): All bits are reset to `0', except bits PL and W remain unchanged * HINT (at offset 0x04E4): All bits remain unchanged * LINT (at offset 0x04F4): Bit 3 (Host to Local Mailbox) is cleared to `0', all other bits remain unchanged * LBUSCFG (at offset 0x04FC): All bits remain unchanged Additional behavior when S = `1' is as follows: * DQ[31:00] is held at high impedance; * Local bus state machine is held in idle; * DMA state machine is held in idle; * PCI bus state machine mastering access is held in idle; and * FIFO are emptied and flags return to default (empty).
0 -- R
This register contains two types of reset bits. The Local Processor Reset bit, R, is intended for use by circuitry connected to the CY7C09449 local bus. The output signals RSTOUTD and RSTOUTD are a direct reflection of the state of this bit. It is intended that RSTOUTD (or its active low version RSTOUTD) be connected to the local processor system's reset. R is set to `1' when the CY7C09449PV reset input is asserted (RST = `0'). After deassertion of RST, R will remain set to `1' until the CY7C09449PV Auto-Configuration process has completed and it has been cleared either via the Auto-Configuration termination control setting or via the PCI bus interface. If RSTOUTD is not used as the local processor system reset, then it can also be cleared via the Local bus interface. The second reset bit is the Soft Reset bit, S. This is used to reset certain internal registers and states of the CY7C09449PV. It is primarily intended for test and debug op-
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CY7C09449PV-AC
Host Interrupt Control and Status Register - HINT0x04E4
31
25 24
16 15
10
9
0
Interrupt Enable Bit 25:16 Interrupt Enable
Interrupt Status Description
Interrupt Enables 0000000000 =no interrupts are enabled (default) xxxxxxxxx1 =I2O Local FIFO overflow interrupt enabled xxxxxxxx1x =I2O PCI FIFO overflow interrupt enabled xxxxxxx1xx =reserved - always read as 0 xxxxxx1xxx =Local to host, mailbox interrupt enabled xxxxx1xxxx =Local to host, external signal interrupt enabled xxxx1xxxxx =DMA complete interrupt enabled xxx1xxxxxx =I2O inbound post FIFO not empty interrupt enabled xx1xxxxxxx =I2O outbound post FIFO not empty interrupt enabled x1xxxxxxxx =PCI target abort interrupt enabled 1xxxxxxxxx =PCI master abort interrupt enabled Note: All enable bits are initially cleared. Interrupt Event Status 0000000000 = no events active xxxxxxxxx1 =I2O Local FIFO overflow xxxxxxxx1x =I2O PCI FIFO overflow xxxxxxx1xx =reserved - always read as 0 xxxxxx1xxx =Local to host mailbox xxxxx1xxxx =Local to host external signal interrupt xxxx1xxxxx =DMA complete xxx1xxxxxx =I2O inbound post FIFO not empty (mirror of I2OLISR[3] - read only at this address) xx1xxxxxxx = I2O outbound post FIFO not empty (mirror of I2OHISR[3] - read only at this address) x1xxxxxxxx = PCI target abort 1xxxxxxxxx = PCI master abort Note: When an event status bit is active, writing a '1' to that bit location will clear the bit except for bits 6 and 7. All event status bits are initially cleared.
9:0 Interrupt Status
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CY7C09449PV-AC
Host to Local Data Mailbox - HLDATA0x04E8
31 25 24 23 16 15 8 7 0
I Bit 24 -- I
Byte 1
Byte 0 Description
Interrupt to Local This bit enables the host to send an interrupt to the Local. When it is set to 1 by the host, it triggers a mailbox interrupt to the local processor. The interrupt remains active until it is cleared by writing to the Local Interrupt Control and Status Register - LINT. 0 = inactive 1 = active This bit is write only. Data byte Two bytes of data that can be written by the host and read by the local processor.
15:8 -- Byte 1 7:0 -- Byte 0
Local Control and Status Registers Local Interrupt Control and Status Register - LINT0x04F4
31
25 24
16 15
10
9
0
Interrupt Enable Bit 25:16 Interrupt Enable
Interrupt Status Description
Interrupt Enables 0000000000 = no interrupts are enabled (default) xxxxxx xxx1 = I2O Local FIFO overflow interrupt enabled xx xxxx xx1x = I2O PCI FIFO overflow interrupt enabled xx xxxx x1xx = reserved - always read as 0 xx xxxx 1xxx = Host to Local mailbox interrupt enabled xx xxx1 xxxx = reserved - always read as 0 xx xx1x xxxx = DMA complete interrupt enabled xx x1xx xxxx = I2O inbound post FIFO not empty interrupt enabled xx 1xxx xxxx = I2O outbound post FIFO not empty interrupt enabled x1 xxxx xxxx = PCI target abort interrupt enabled 1x xxxx xxxx = PCI master abort interrupt enabled Note: All enable bits are initially cleared. Interrupt Event Status 00 0000 0000 = no events active xx xxxx xxx1 = I2O Local FIFO overflow xx xxxx xx1x = I2O PCI FIFO overflow xx xxxx x1xx = reserved - always read as 0 xx xxxx 1xxx = Host to Local mailbox xx xxx1 xxxx = reserved - always read as 0 xx xx1x xxxx = DMA operation complete xx x1xx xxxx = I2O inbound post FIFO not empty (mirror of I2OLISR[3] - read only at this address) xx 1xxx xxxx = I2O outbound post FIFO not empty (mirror of I2OHISR[3] - read only at this address) x1 xxxx xxxx = PCI target abort 1x xxxx xxxx = PCI master abort Note: When an event status bit is active, writing a '1' to that bit location will clear the bit except for bits 6 and 7. All event status bits are initially cleared.
9:0 Interrupt Status
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CY7C09449PV-AC
Local to Host Data Mailbox - LHDATA0x04F8
31 25 24 23 16 15 8 7 0
I
Byte 1
Byte 0
Bit 24 -- I
Description Interrupt to Host When this bit is written to 1 by the local processor, it causes a mailbox interrupt to the host. The interrupt will remain active until it is cleared by the host in the Host Interrupt Control and Status Register - HINT 0 = inactive 1 = active This bit is write only. Data bytes Two bytes of data written by the local and read by the host processor.
15:8 -- Byte 1 7:0 -- Byte 0
Local Bus Configuration Register - LBUSCFG0x04FC
31 21 20 0
Local Bus Configuration Bit 20 19 18 17 16 15 Description LINE_WRAP_DIS: Defines the enable for cache line wrapping. 0 = Enable cache line wrapping (default)1 = Disable cache line wrapping RDY_IN_FALL: Defines the edge of CLKIN used to sample the RDY_IN and RDY_IN input signals. 0 = Rising Edge (default)1 = Falling Edge SELECT_POL: Defines the polarity of the SELECT input signal. 0 = Active LOW (default)1 = Active HIGH SELECT_FALL: Defines the edge of CLKIN used to sample the SELECT input signal. 0 = Rising Edge (default)1 = Falling Edge RDY_OUT_OE: Defines the three-state mode of the RDY_OUT output signal. 0 = Drive all of the time.1 = Drive only when asserted active. (default) XTND_RDY_OUT: Defines the RDY_OUT output signal relation to the final data phase. 0 = Normal. RDY_OUT goes inactive after the final data phase (default) 1 = Extended Ready Out. RDY_OUT remains active after the final data phase until the internal address strobe (typically STROBE) goes inactive. (see field RWMODE for the defining characteristics of the Internal Address Strobe). -- DO NOT set XTND_RDY_OUT = 1 when BLASTMODE = 1. BURST_STYLE: Defines the data ordering protocol of bursts on the local bus. 0 = normal linear bursts (default)1 = 486 style burst (byte ordering in a burst is 048C; 40C8; 8C04; C840) INT_POL: Defines the polarity of the IRQ_OUT output signal. 0 = Active LOW interrupt to the local processor (default)1 = Active HIGH interrupt to the local processor BLAST_POL: Defines the polarity of the BLAST input signal. 0 = Active LOW (default)1 = Active HIGH ALE_POL: Defines the polarity of the ALE input signal. 0 = Active LOW1 = Active HIGH (default) RDYOUT_POL: Defines the polarity of the RDY_OUT output signal. 0 = Active LOW (default)1 = Active HIGH BW: Defines the data bus width of the local processor interface. 00 = 8 bit10 = 32 bit 01 = 16 bit11 = 32 bit with encoded byte enables per Motorola protocol (default) BLASTMODE: Determines the function of the BLAST input signal. 0 = BLAST is active only during the last transaction of the burst (default) 1 = BLAST is active throughout the entire burst, and goes inactive when with RDY_IN or RDY_IN become inactive on the last read or write of the burst. -- DO NOT set BLASTMODE = 1 when XTND_RDY_OUT = 1. BEMODE: Determines the byte enable encoding for 16 and 32 bit Motorola modes. 0 = normal byte enables1 = Motorola byte enable encoding. (default) Page 39 of 50
14 13 12 11 10 9:8
7
6
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CY7C09449PV-AC
Bit 5:4 Description RWMODE: Defines how the READ, WRITE, and address STROBE input signals are interpreted internally and defines the Internal Address Strobe. The active polarity of STROBE is determined by ASMODE. `01' is default. Pin Name READ WRITE STROBE 3:2 RWMODE = 00 W_R Not Used Internal Address Strobe RWMODE = 01 Not Used R_W Internal Address Strobe RWMODE = 1X READ data; used as Internal Strobe WRITE data; used as Internal Strobe Not used as Internal Address Strobe
ASMODE: Bit 2 defines the polarity of STROBE input signal. And bit 3 defines the edge of CLKIN used to sample the Internal Address Strobe (see field RWMODE for a defining characteristic of the Internal Address Strobe) x0 = STROBE is active LOW (default)x1 = STROBE is active HIGH 0x = Internal Address Strobe rising edge sampled (default)1x = Internal Address Strobe falling edge sampled DDIN: Delayed Data Input -- Defines protocol for validated input data. 0 = input data is valid during the current cycle when RDY_IN, RDY_IN, and RDY_OUT are active. (default) 1 = input data is valid one cycle after when RDY_IN, RDY_IN, and RDY_OUT are active. DDOUT: Delayed Data Output -- Defines protocol for validated output data. 0 = output data is valid during current cycle when RDY_IN, RDY_IN, and RDY_OUT are active. (default) 1 = output data is valid one cycle after when RDY_IN, RDY_IN, and RDY_OUT are active.
1
0
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CY7C09449PV-AC
Performance Characteristics
Absolute Maximum Ratings [4] Storage Temperature .................................. -55C to +125C Ambient Temperature Under Bias................. -40C to +85C Max Operating Current (IDD)[5,6] ................................250 mA Voltage on Any VDD Pin Referenced to VSS .. -0.5V to +4.0V Voltage on Any Signal Pin Referenced to VSS-0.5V to +7.0V Recommended Operating Environment Ambient Operating Temperature................... TA0C to +70C Supply Voltage .........................................VDD+3.0V to +3.6V Ground Voltage Reference .......................................VSS0.0V FCLK (PCI Clock Input Frequency)...... CLK0 MHz to 33 MHz FCLKIN (Local Bus Clock Input Frequency)[7] ...CLKIN0 MHz to 50 MHz Parameter VIH VIL VIPU IIL VOH VOL CIN CCLK CIDSEL LPIN Description Input High Voltage Input Low Voltage Input Pull-up Voltage Input Leakage Current Output High Voltage Output Low Voltage Input Pin Capacitance CLK Pin Capacitance IDSEL Input Pin Capacitance Pin Inductance 5
[8]
Recommended Operating DC Parameters--PCI Bus Signals The CY7C09449PV is compatible with the PCI requirements for 3.3V and 5V signaling. Refer to the PCI Local Bus Specification, Revision 2.2, as published by the PCI Special Interest Group; the URL is http://www.pcisig.com/ Due to the 5V tolerant nature of the I/O, the I/O are not clamped to VDD. Operation of the CY7C09449PV in a PCI 5V signaling environment is electrical and timing compatible with the PCI specification. In a 3.3V signaling environment, all PCI requirements are met except for the output 3.3V clamp, which is in direct conflict with 5V tolerance. The CY7C09449PV complies with the PCI AC specifications.
Condition
Min. 0.5VDD -0.5 0.7VDD
Max. +5.75V 0.3VDD 10
Unit V V V A V V pF pF pF nH
0 < VIN < VDD IOUT = -0.5 mA IOUT = 1.5 mA 0.9VDD
0.1VDD 10 12 8 20
Recommended Operating DC Parameters--Local Signals The recommended operating DC parameters for the local bus are specified here. Parameter VIH VIL IIL VOH VOL CIN CCLK LPIN Description Input High Voltage Input Low Voltage Input Leakage Current Output High Voltage Output Low Voltage Input Pin Capacitance CLK Pin Capacitance Pin Inductance 5 0 < VIN < VDD IOUT = -0.8 mA IOUT = 0.8 mA 2.4 0.5 10 12 20 Condition Min. 2.0 -0.5 Max. 5.75 0.8 10 Unit V V A V V pF pF nH 8 Notes
Notes: 4. The voltage on any input or I/O pin can not exceed the power pin during power-up. 5. CLK=33 MHz, CLKIN = 50 MHz, PCI and Local buses operating at 25% duty cycle. 6. Also see Operating Power Characteristics section (Page 45). 7. For proper initialization, CLKIN must toggle more than 300,000 cycles after RST has been deasserted. 8. Except that INTA is an open drain output. 9. Except that IRQ_OUT is an open drain output.
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CY7C09449PV-AC
Timing Parameters--PCI Bus Signals The CY7C09449PV is compliant with the PCI timing requirements for 3.3V and 5V signaling. Refer to the PCI Local Bus Specification, Revision 2.2, as published by the PCI Special Interest Group; the URL is http://www.pcisig.com/ Parameter tCYC tHIGH tLOW tVAL tVAL(REQ) tON tOFF tSU tSU(GNT) tHOLD tRST tRST-CLK tRST-OFF tRST-FPCA tRHI-FFA CLK Cycle Time CLK High Time CLK Low Time CLK Slew Rate CLK to Output for Bused Signals[11] CLK to Output for REQ
[11] [10]
Description
Min. 30 11 11 1 2 2 2
Max.
Unit ns ns ns
4 11 12 28
V/ns ns ns ns ns ns ns ns mV/ns ms s
Float to Active Delay from CLK Active to Float Delay from CLK Input Set-up Time to CLK for Bused Signals Input Set-up Time to CLK for GNT Input Hold Time to CLK RST Slew Rate[12] RST Active Time after Power Stable RST Active Time after CLK Stable RST Active to Output Float Delay RST High to First PCI Configuration Access RST High to First FRAME Assertion
[13]
7 10 0 50 1 100 40 225 5
ns clocks clocks
Timing Parameters--CY7C09449PV Buffered PCI Clock and Reset The CY7C09449PV provides copies of the PCI clock input, CLK, on the PCLKOUT[2:0] pins. The system level function and timing of these outputs are the same as those of the CLK input. The CY7C09449PV also provides a registered copy of the PCI reset input, RST, on the RSTOUT pin. The PCI reset is synchronized to the Local bus clock, CLKIN. RSTOUT will follow RST by no more than two CLKIN cycles. The detailed timing characteristics of the PCLKOUT[2:0] and RSTOUT signal outputs is shown below. Parameter tPCLKOUT tRSTOUT PCLKOUT Delay from CLK CLKIN to RSTOUT Valid
[14]
Description
[14]
Min. 2 2
Max. 10 10
Units ns ns
Notes: 10. Clock frequency may range from nominal DC to 33 MHz. The clock frequency may change at anytime, but must not violate other parameters of this specification: clock edges must remain monotonic and within the specified CLK Slew Rate and clock high and low times must be no shorter than specified CLK High and CLK Low Times. 11. Output maximum times are evaluated with CL = 50 pF. Output minimum times are evaluated with CL = 0 pF. Actual test capacitance may vary, but results are correlated to these loads. 12. Specification only applies to rising (deasserted) edge of RST. 13. RST is asserted and deasserted asynchronously to CLK. 14. 50-pF load.
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CY7C09449PV-AC
CLK
tPCLKOUT tPCLKOUT
PCLKOUT[2:0]
CLKIN
tRSTOUT tRSTOUT
RSTOUT#
Timing Parameters -- Local Bus Signals The parameters for the local bus are specified here. Parameter tLOCAL tHIGH tLOW tSU tHOLD tOUT tON_DQ tOUT_DQ tOFF_DQ tSU_ADR tH_ADR tSU_ALE tH_ALE tMIN_ALE CLKIN High Time CLKIN Low Time
[16]
Description CLKIN Cycle Time (Local clock)
[16] [15]
Min. 20 40 40 8 3 2 2 2 2 6 3 1 3 5
Max. 60 60
Unit ns % % ns ns
Input Set-up Time to CLKIN[17] Input Hold Time to CLKIN CLKIN to Output Valid
[18]
10 14 10 14
ns ns ns ns ns ns ns
DQ[31:0] Float to Active Delay from CLKIN DQ[31:0] Output Delay from CLKIN DQ[31:0] Active to Float Delay from CLKIN ADR[14:2] Input Set-up Time to CLKIN ADR[14:2] Input Hold Time from CLKIN ADR[14:2] Input Set-up Time to ALE ADR[14:2] Input Hold Time from ALE Minimum Active Pulse width for ALE
[19]
Notes: 15. VTEST = 1.5V. 16. Voltage threshold for HIGH is 2.0V; Voltage threshold for LOW is 0.8V. 17. Inputs are STROBE, SELECT, READ, WRITE, RDY_IN, RDY_IN, BE[3:0], DQ[31:0], BLAST, and IRQ_IN. 18. CL = 50 pF. Outputs are RDY_OUT, IRQ_OUT, RSTOUTD, and RSTOUTD. 19. Voltage threshold for HIGH is 2.0V.
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CY7C09449PV-AC
tLOCAL
CLKIN
tHIGH tLOW
INPUTS
tSU
tHOLD
OUTPUTS
tOUT tOUT_DQ
DQ[31:0]
tON_DQ tOFF_DQ
ALE
tSU_ADR
tMIN_ALE tSU_ALE
ADR[14:2]
tH_ADR tH_ALE
Timing Parameters--I2C Serial Port Bus Signals The I2C-compatible serial interface is designed for a 100-Kb transfer rate. The interface clock is referenced to the local clock, CLKIN. The table below gives the parameters of the CY7C09449PV's I2C-compatible serial interface with respect to the number of local clock periods and the equivalent number of microseconds if the clock is run at 50 MHz. The 100-Kbit/s rate is accomplished with a CLKIN rate of 50 MHz. For CLKIN rates other than 50 MHz, use the Minimum Clocks column to calculate the Minimum Time for each parameter. Minimum Clocks (Clock Periods) 250 250
[20, 21]
Parameter tSCL_LO tSCL_HI tBUF tSU_STA tHD_STA tSU_DAT tHD_DAT tSU_STO Low Period of SCL High Period of SCL
Description
Minimum Time (microseconds) 5.00 5.00 10.00 5.00 5.00 2.50 5.00 5.00
Bus Free Time between 'Start' & 'Stop' Set-up Time for Repeated 'Start'[20] Hold Time for 'Start' Set-up Time for Data Hold Time for Data Set-up time for 'Stop'
500 250 250 125 125 250
Notes: 20. 'Start' condition is a HIGH-to-LOW transition on SDA while SCL is HIGH. 21. 'Stop' condition is a LOW-to-HIGH transition on SDA while SCL is HIGH
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CY7C09449PV-AC
tHD_STA
tBUF DATA
SDA
tSU_DAT
tHD_DAT
~
tSU_STO
tSU_STA
SCL
tSCL_LO tSCL_HI
Operating Power Characteristics Operating power and currents for the CY7C09449PV at typical environment are specified here, VDD = +3.3V, Temp. = +25C. Parameter PD IDD IDD_LSTATIC IDD_STATIC Description Power Dissipation
[22] [22] [23]
Condition
Max. 720 200 40 1
Unit mW mA mA mA
Operating Current Static, no clocks
Static Local Bus Clock
Notes: 22. CLK = 33 MHz, CLKIN = 50 MHz, PCI and Local buses operating at 25% duty cycle. This value is typical. 23. CLK = 33 MHz, CLKIN = 0 MHz, PCI and Local buses are inactive. Note that for proper initialization of the CY7C09449PV, CLKIN must toggle for some number of cycles after RST# is de-asserted. See the section Recommended Operating Environment for the specification of the CLKIN toggle parameter.
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CY7C09449PV-AC
CY7C09449PV Operations
Local Bus Configurations The CY7C09449PV interfaces to several processor families. Local bus configurations words for some processors are indicated here. These may not be suitable for all applications for a given processor. The specific application's local processor subsystem architecture may impact some parameters of the local bus configuration word. The 21-bit Local Bus Configuration Operations register, LBUSCFG, can be written via the I2C serial interface upon chip initialization to prepare the CY7C09449PV local bus for the proper interface protocol. Processor Motorola Power QUICC MPC860 (default) Motorola QUICC 68360 Motorola 68040 (default) Intel i960 Intel i486 Intel 80186 Hitachi SH7708 Hitachi H8/3048 Texas Instruments TMS320LC31 PCI Bus Mastering Burst transfers between the CY7C09449PV 16-KB shared memory and the PCI bus system are performed by the direct memory access (DMA) controller. Set-up for the DMA controller is accomplished by programming the Operations Registers of the CY7C09449PV from either the PCI bus interface or the Local bus interface. An indication of a completed DMA is available by polling an Operations register or servicing an interrupt. Ownership of the DMA controller by either the PCI or Local bus interfaces is arbitrated by software using the Operations Registers. The address and transfer size registers operate with DWORD resolution. The lower two bits of each of the address and transfer size fields are ignored. Transfers over the PCI bus are DWORD so all four byte enables of the bus are active when transferring data mastered by the CY7C09449PV. The full 32bit PCI address space is supported by the DMA controller. The direction of transfer is determined by the 'W' bit in the DMA Control Register. 'W' is the "Write" bit and is with respect to the CY7C09449PV "writing" to the PCI bus. The basic sequence to setup a DMA is as follows: 1. Enable the Interrupt Mask for the desired interface if an interrupt on DMA completion is required (e.g., LINT[21] = 1 will enable the interrupt onto the IRQ_OUT pin). 2. Load the address for the beginning of the transfer block of CY7C09449PV shared memory. This is the DMA Local Base Address Register, DMALBASE. 3. Load the address for the beginning of the transfer block of PCI bus space. This is the DMA Host Base Address Register, DMAHBASE. 4. Load the size of the transfer block. This is the DMA Size Register, DMASIZE. 5. To initiate the DMA, a write to the least significant byte of the DMA Control Register, DMACTL, will start the controller. Document #: 38-06061 Rev. *A LBUSCFG value 0x010B50 0x018B18 0x010B50 0x010A00 0x016A00 0x012D21 0x010E11 0x010D00 0x010A91 Writing a '1' to bit 0 will transfer data from the CY7C09449PV shared memory, (pointed to by DMALBASE), to the PCI bus space, (pointed to by DMAHBASE). This causes write bursts on the PCI bus. Writing a '0' to bit 0 will transfer the other direction and cause read bursts on the PCI bus. The CY7C09449PV bus mastering logic will use the most efficient PCI command available for all of its bursts during the transfer. 6. When the DMA is complete, LINT[5] will be set. If interrupts are enabled for DMA completions, then an interrupt will be generated. If not, LINT[5] can be polled. An additional option of a PCI bus mastered read transfer involves setting the option to perform non-prefetchable PCI reads during transfers into CY7C09449PV shared memory. This option is set in the DMA Control Register with the PFI flag. Also, ownership of the controller can be arbitrated in software with assistance of the L and P bits in the DMA Control Register; these are the Local Bus Ownership and PCI Bus Ownership flags, respectively. See the section CY7C09449PV Operations Registers for details. I2O Message Unit The I2O Specification describes a messaging unit consisting of four FIFOs, a shared memory to store message frames, and an interrupt function. The structure of this unit is described in the I2O Architecture Specification, version 1.5 on pages 4-2 through 4-7. This capability is fully integrated within the CY7C09449PV. Reference URL: http://www.i2osig.org/ There is no need for external circuitry to manage the FIFO operations. If I2O functionality is not desired, then the FIFOs are available for general purpose use. Each of the four FIFO are 32 DWORD deep, are accessible from both the PCI and Local bus interfaces, and can generate interrupts to both bus interfaces. The unit operates in two clock domains, that of the PCI bus and that of the Local bus. I2O message frames for transfer between the PCI and the Local domains are located within the 16-Kbyte CY7C09449PV Shared Memory, which is a generalpurpose dual-port memory. There is no restriction upon where in the 16-Kbyte space that the message frames reside, however, to satisfy I2O requirements, the message frames must begin at DWORD boundaries. Neither bus's access is dependent upon the operational state of the other bus. This is governed by the nature of the CY7C09449PV Shared Memory. Operations of the I2O FIFO and the I2O Interrupt functions occur completely within the clock domain of the Local bus, however access is available to both the PCI and Local bus interfaces. From a system perspective, the following diagram illustrates the I2O Message Unit transfer function supported by the CY7C09449PV. The CY7C09449PV is represented by the "Message Queues" block of the diagram and consists of both Inbound and Outbound Queues and the Shared Memory. For more description of the terminology used in the diagram, refer to the I2O Architecture Specification. Reference URL: http:// www.i2osig.org/ Direct Access Direct Access allows the local processor to access the PCI bus directly, bypassing the shared memory. In this mode the local processor can generate the following PCI bus master cycles: * Configuration Read C/BE[3:0] = 0xA Page 46 of 50
CY7C09449PV-AC
0 -- Target Initializes Free List with Message Frame Addresses, (MFA) 1 -- Initiator Gets Free MFA 2 -- Initiator Transfers Message Into Message Frame Storage Area 3 -- Initiator Completes Transfer and Signals Target by Posting MFA 4 -- Target is Notified When Post List Becomes Non-Empty 5 -- Target Gets MFA of Posted Messag
HOST
6 -- Target Transfers Message Out of Message Frame Storage Area 7 -- Target Completes Transfer by Retur MFA to Free List PCI BUS
SYSTEM BUS
HOST IS INITIATOR (OR ANOTHER IOP)
MESSAGE QUEUES INBOUND QUEUE
FREE LIST FIFO OF MFA POST LIST FIFO OF MFA INBOUND MESSAGE FRAMES
MFA = OFFSET FROM START OF IOP SHARED MEMORY
OUTBOUND QUEUE
OUTBOUND MESSAGE FRAMES MFA = SYSTEM ADDRESS POST LIST FIFO OF MFA FREE LIST FIFO OF MFA
OUTBOUND QUEUE PROCESSING
INBOUND QUEUE PROCESSING
0
7
5
4
SHARED MEMORY
3
1
6
2
I/O DEVICES
IOP
PROCESSOR
QUEUES.VSD DB 7/15/9
* Configuration Write C/BE[3:0] = 0xB * I/O Read C/BE[3:0] = 0x2 * I/O Write C/BE[3:0] = 0x3 * Memory Read C/BE[3:0] = 0x6 * Memory Write C/BE[3:0] = 0x7 * Special Cycle C/BE[3:0] = 0x1 * Interrupt Acknowledge C/BE[3:0] = 0x0 To operate in this mode, the local processor programs the Direct Access register. Programming sets the base address for the PCI master access and the type of PCI command to be generated. Then the local processor writes to the Direct Access space of the CY7C09449PV Memory Map. Offsets into the Direct Access region of the memory map are added to the PCI base address of the Direct Access register and become the address for the PCI bus master access. The type of PCI command generated is defined in the Direct Access register. A local bus read to the Direct Access area of the memory map becomes a PCI bus master read. Likewise, a local bus write to the memory map becomes a PCI bus master write. Host Bridge The CY7C09449PV can be used as a host bridge. The processor on the CY7C09449PV Local bus is therefore the host processor in the system. A host processor configures the other PCI devices on the PCI bus. The CY7C09449PV provides the I2C Serial Port and Auto-Configuration mechanism to setup for host bridge operations. Most aspects of Auto-Configuration apply to non-host use of the CY7C09449PV, as well. The CY7C09449PV must master cycles onto the PCI bus to be a host bridge. The Master Enable bit located in the PCI Document #: 38-06061 Rev. *A
configuration space is the means to enable CY7C09449PV PCI mastering. Since the CY7C09449PV's default value for the Master Enable bit is deasserted, it is necessary to use the CY7C09449PV Auto-Configuration mechanism to enable PCI mastering. During the power-up reset sequence, the I2C serial interface loads data from a non-volatile memory (typically a serial EEPROM) to set the Master Enable bit in the PCI configuration space. Some, but not all, of the PCI configuration values are loaded using this mechanism. These values can be read by other devices in the system to identify the host bridge, (e.g., Device ID, Vendor ID, Class Code, etc.). Another part of the Auto-Configuration mechanism is to setup the Local bus interface with the host processor and, optionally, provide reset control to the host processor. The Local Bus Configuration register is loaded from the serial EEPROM image. This will set the protocol of the Local interface. The Host Control register is loaded by the Auto-Configuration mechanism and can control reset to the host processor. Utilization of the CY7C09449PV RSTOUTD output signal, (or its complement, RSTOUTD), is how the CY7C09449PV can control host processor reset. The Host Control register image is stored in the serial EEPROM and indicates if the reset will remain asserted or will release after Auto-Configuration is complete. Normally, it should release the host from reset. If it is not released, then an external PCI master will be required to release the host processor. Finally, the CY7C09449PV uses the Direct Access function to configure PCI devices on the PCI bus. The first device that it configures is typically itself. It is important that the Master Enable bit is set. Without this bit asserted, the CY7C09449PV
IOP IS INITIATOR
IOP IS TARGET
HOST IS TARGET
1
3
2
6
4
5
7
0
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CY7C09449PV-AC
cannot configuration itself (or any other devices) via the PCI bus. Dual-Port Shared Memory In order to perform concurrent target access to shared memory from the PCI and Local bus interfaces it is generally necessary to devise a handshake protocol and/or address access allocation scheme to prevent corrupting memory locations. That is, a location within the CY7C09449PV dual-port memory may be corrupted if a read from one interface occurs simultaneously with a write from the other interface to that same location. The CY7C09449PV assists the user in managing concurrent access to the shared memory. The CY7C09449PV PCI and Local bus are high performance interfaces. Internal logic performs read pre-fetching in order to maintain a full speed, zero wait-state, burst access to the shared memory. For managing memory access, the CY7C09449PV performs a disconnect or wait for target reads at each 64-byte boundary. If a user is allocating sections of memory to PCI and Local space and intends to execute simultaneous access to the shared memory from both interfaces, then this 64-byte boundary can be used to place PCI and Local sections of memory adjacent to each other. In other words, the CY7C09449PV has special logic that detects incoming burst addresses and will initiate the disconnect or wait at each 64byte boundary. In this way, if the transaction is to end at the boundary, then no further pre-fetching occurs since time has been given to the master to end the bus transaction. For the PCI bus, this is performed by a target disconnect. For the Local bus, this is wait states.
Ordering Information
Ordering Code CY7C09449PV-AC Package Name TQFP160 Package Type 160-Pin Plastic Thin Quad Flat Pack Operating Range 0C to +70C
Package Diagram
Pin 160 Pin 1
Document #: 38-06061 Rev. *A
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CY7C09449PV-AC
Package Diagram (continued)
Document #: 38-06061 Rev. *A
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(c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C09449PV-AC
Document Title: CY7C09449PV-AC 128Kb Dual-Port SRAM with PCI Bus Controller (PCI-DP) Document Number: 38-06061 REV. ** *A ECN NO. 113168 122309 Issue Date 02/14/02 12/27/02 Orig. of Change DSG RBI Description of Change Change from Spec number: 38-01014 to 38-05172 Change from Spec number: 38-05172 to 38-06061 Power up requirements added to Absolute Maximum Ratings Information
Document #: 38-06061 Rev. *A
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